On Sun, Apr 8, 2012 at 5:09 PM, Ouabache Designworks <[email protected]> wrote: > > > On Sat, Apr 7, 2012 at 11:07 PM, Richard Herveille <[email protected]> > wrote: >> >> Somehow I thought this was always the case, or always the intended >> behaviour. This is what was agreed with Damjan 10years ago. >> First action of the bootup code is to clear R0 and invalidate the MMU and >> Cache registers. After that the CPU should be ready for normal >> bootup-sequence. > > > The issue is that you can reset the cpu so that it always powers up with a 0 > in R0 and the caches and mmus invalidated with very little cost or effort. > You are putting a critical requirement on the firmware designer that is > non-obvious and hard to debug. Our goal is to make this cpu easy to use. > Spending a few hours chasing a problem that turned out to be that you forgot > to clear R0 is not going to help anyone. >
It's not very little cost - it'd be a counter and a small FSM and some extra MUXing everywhere we have a RAM (2 RAMs for each cache and MMU, that's 8 instances of this logic for a standard OR1200) for single-shot use at reset. It's way too much to pay to protect from poorly written initialisation code. I accept we should be making things easy to use, and we do by clearly documenting how to bring it up. I've posted my proposed change to the architecture spec on the wiki: http://opencores.org/or1k/Architecture_Specification#GPR0_usage.2C_implementation Cheers Julius _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
