This patch adds the altera de1 board to the orpsoc git repository maitained by Stefan (git://openrisc.net/stefan/orpsoc).
It is fully based on the de2_115 port. Franck Jullien (1): Add Altera de1 board port boards/altera/de1/Makefile.inc | 77 + boards/altera/de1/README | 31 + boards/altera/de1/backend/rtl/verilog/pll.v | 349 + boards/altera/de1/bench/verilog/include/eth_stim.v | 1453 + .../verilog/include/orpsoc-testbench-defines.v | 2 + .../de1/bench/verilog/include/synthesis-defines.v | 2 + .../altera/de1/bench/verilog/include/timescale.v | 41 + boards/altera/de1/bench/verilog/orpsoc_testbench.v | 607 + boards/altera/de1/bench/verilog/spi_slave.v | 92 + .../de1/rtl/verilog/adv_debugsys/adbg_crc32.v | 117 + .../de1/rtl/verilog/adv_debugsys/adbg_jsp_biu.v | 530 + .../de1/rtl/verilog/adv_debugsys/adbg_jsp_module.v | 574 + .../de1/rtl/verilog/adv_debugsys/adbg_or1k_biu.v | 299 + .../rtl/verilog/adv_debugsys/adbg_or1k_module.v | 729 + .../verilog/adv_debugsys/adbg_or1k_status_reg.v | 195 + .../de1/rtl/verilog/adv_debugsys/adbg_wb_biu.v | 440 + .../de1/rtl/verilog/adv_debugsys/adbg_wb_module.v | 793 + .../de1/rtl/verilog/adv_debugsys/adv_dbg_if.v | 449 + .../altera/de1/rtl/verilog/adv_debugsys/bytefifo.v | 225 + .../altera/de1/rtl/verilog/adv_debugsys/syncflop.v | 126 + .../altera/de1/rtl/verilog/adv_debugsys/syncreg.v | 158 + boards/altera/de1/rtl/verilog/arbiter/README | 67 + .../de1/rtl/verilog/arbiter/arbiter_bytebus.v | 1192 + .../altera/de1/rtl/verilog/arbiter/arbiter_dbus.v | 1269 + .../altera/de1/rtl/verilog/arbiter/arbiter_ibus.v | 337 + boards/altera/de1/rtl/verilog/clkgen/clkgen.v | 186 + boards/altera/de1/rtl/verilog/flashrom/README | 14 + boards/altera/de1/rtl/verilog/flashrom/flashrom.v | 68 + boards/altera/de1/rtl/verilog/gpio/README | 7 + boards/altera/de1/rtl/verilog/gpio/gpio.v | 175 + .../altera/de1/rtl/verilog/include/adbg_defines.v | 75 + .../de1/rtl/verilog/include/adbg_or1k_defines.v | 89 + .../de1/rtl/verilog/include/adbg_wb_defines.v | 92 + .../de1/rtl/verilog/include/dbg_cpu_defines.v | 85 + .../altera/de1/rtl/verilog/include/dbg_defines.v | 153 + .../de1/rtl/verilog/include/dbg_wb_defines.v | 113 + .../de1/rtl/verilog/include/ethmac_defines.v | 255 + .../rtl/verilog/include/i2c_master_slave_defines.v | 66 + .../de1/rtl/verilog/include/or1200_defines.v | 1823 + .../de1/rtl/verilog/include/orpsoc-defines.v | 136 + .../altera/de1/rtl/verilog/include/orpsoc-params.v | 211 + boards/altera/de1/rtl/verilog/include/sd_defines.v | 89 + .../altera/de1/rtl/verilog/include/tap_defines.v | 69 + .../altera/de1/rtl/verilog/include/uart_defines.v | 250 + .../rtl/verilog/include/usbhostslave_constants_h.v | 32 + .../verilog/include/usbhostslave_hostcontrol_h.v | 75 + .../rtl/verilog/include/usbhostslave_hostslave_h.v | 80 + .../include/usbhostslave_serialinterfaceengine_h.v | 108 + .../verilog/include/usbhostslave_slavecontrol_h.v | 86 + .../verilog/include/usbhostslave_wishbonebus_h.v | 35 + .../altera/de1/rtl/verilog/orpsoc_top/orpsoc_top.v | 2681 ++ .../altera/de1/rtl/verilog/sdc_controller/sd_bd.v | 200 + .../rtl/verilog/sdc_controller/sd_clock_divider.v | 46 + .../de1/rtl/verilog/sdc_controller/sd_cmd_master.v | 325 + .../verilog/sdc_controller/sd_cmd_serial_host.v | 577 + .../rtl/verilog/sdc_controller/sd_controller_wb.v | 311 + .../de1/rtl/verilog/sdc_controller/sd_crc_16.v | 48 + .../de1/rtl/verilog/sdc_controller/sd_crc_7.v | 34 + .../rtl/verilog/sdc_controller/sd_data_master.v | 514 + .../verilog/sdc_controller/sd_data_serial_host.v | 464 + .../rtl/verilog/sdc_controller/sd_fifo_rx_filler.v | 102 + .../rtl/verilog/sdc_controller/sd_fifo_tx_filler.v | 126 + .../de1/rtl/verilog/sdc_controller/sd_rx_fifo.v | 121 + .../de1/rtl/verilog/sdc_controller/sd_rx_fifo_tb.v | 128 + .../de1/rtl/verilog/sdc_controller/sd_tx_fifo.v | 72 + .../rtl/verilog/sdc_controller/sdc_controller.v | 495 + .../de1/rtl/verilog/versatile_mem_ctrl/Makefile | 77 + .../de1/rtl/verilog/versatile_mem_ctrl/README | 171 + .../versatile_mem_ctrl/rtl/verilog/Makefile | 65 + .../versatile_mem_ctrl/rtl/verilog/async_fifo_mq.v | 110 + .../rtl/verilog/burst_length_counter_defines.v | 42 + .../rtl/verilog/cke_delay_counter_defines.v | 41 + .../verilog/versatile_mem_ctrl/rtl/verilog/codec.v | 124 + .../versatile_mem_ctrl/rtl/verilog/copyright.v | 41 + .../rtl/verilog/ctrl_counter_defines.v | 42 + .../versatile_mem_ctrl/rtl/verilog/dcm_pll.v | 249 + .../versatile_mem_ctrl/rtl/verilog/ddr_16.fzm |37120 ++++++++++++++++++++ .../rtl/verilog/ddr_16_defines.v | 127 + .../versatile_mem_ctrl/rtl/verilog/ddr_ff.v | 135 + .../verilog/versatile_mem_ctrl/rtl/verilog/delay.v | 31 + .../versatile_mem_ctrl/rtl/verilog/dff_sr.v | 59 + .../versatile_mem_ctrl/rtl/verilog/egress_fifo.v | 365 + .../verilog/versatile_mem_ctrl/rtl/verilog/fifo.v | 462 + .../rtl/verilog/fifo_adr_counter_defines.v | 41 + .../versatile_mem_ctrl/rtl/verilog/fifo_fill.fzm |10815 ++++++ .../versatile_mem_ctrl/rtl/verilog/fizzim.pl | 2326 ++ .../versatile_mem_ctrl/rtl/verilog/fsm_sdr_16.v | 412 + .../versatile_mem_ctrl/rtl/verilog/fsm_wb.v | 116 + .../versatile_mem_ctrl/rtl/verilog/gray_counter.v | 75 + .../versatile_mem_ctrl/rtl/verilog/inc_adr.v | 70 + .../rtl/verilog/latency_counter_defines.v | 42 + .../rtl/verilog/pre_delay_counter_defines.v | 42 + .../versatile_mem_ctrl/rtl/verilog/ref_counter.v | 118 + .../rtl/verilog/ref_counter_defines.v | 41 + .../rtl/verilog/ref_delay_counter_defines.v | 42 + .../versatile_mem_ctrl/rtl/verilog/sdr_16.fzm |19678 +++++++++++ .../rtl/verilog/sdr_16_defines.v | 71 + .../rtl/verilog/versatile_counter.xls | Bin 0 -> 14336 bytes .../rtl/verilog/versatile_fifo_async_cmp.v | 129 + .../verilog/versatile_fifo_dual_port_ram_dc_sw.v | 32 + .../rtl/verilog/versatile_mem_ctrl_ddr.v | 507 + .../rtl/verilog/versatile_mem_ctrl_defines.v | 19 + .../rtl/verilog/versatile_mem_ctrl_ip.v | 5460 +++ .../rtl/verilog/versatile_mem_ctrl_top.v | 754 + .../rtl/verilog/versatile_mem_ctrl_wb.v | 157 + .../versatile_mem_ctrl/versatile_mem_ctrl.v | 2767 ++ .../rtl/vhdl/adv_debugsys/altera_virtual_jtag.vhd | 158 + boards/altera/de1/sim/bin/Makefile | 83 + boards/altera/de1/sim/run/Makefile | 1 + boards/altera/de1/sw/Makefile.inc | 25 + boards/altera/de1/sw/board/include/board.h | 119 + boards/altera/de1/sw/bootrom/Makefile | 27 + boards/altera/de1/sw/drivers/usbhostslave/Makefile | 10 + .../usbhostslave/include/usbhostslave-host.h | 383 + .../usbhostslave/include/usbhostslave-slave.h | 153 + .../sw/drivers/usbhostslave/usbhostslave-host.c | 47 + .../sw/drivers/usbhostslave/usbhostslave-slave.c | 129 + .../de1/sw/tests/i2c_master_slave/sim/Makefile | 15 + .../sim/i2c_master_slave-loopback.c | 207 + .../altera/de1/sw/tests/usbhostslave/sim/Makefile | 15 + .../usbhostslave/sim/usbhostslave-hostsimple.c | 410 + .../usbhostslave/sim/usbhostslave-slavesimple.c | 309 + boards/altera/de1/syn/quartus/bin/Makefile | 157 + boards/altera/de1/syn/quartus/run/Makefile | 2 + boards/altera/de1/syn/quartus/sdc/JTAG_DEBUG.sdc | 1 + boards/altera/de1/syn/quartus/sdc/common.sdc | 12 + .../tcl/GENERIC_JTAG_TAP_pin_assignments.tcl | 8 + .../de1/syn/quartus/tcl/GPIO0_pin_assignments.tcl | 16 + .../de1/syn/quartus/tcl/UART0_pin_assignments.tcl | 4 + .../tcl/VERSATILE_SDRAM_pin_assignments.tcl | 87 + .../de1/syn/quartus/tcl/common_pin_assignments.tcl | 4 + boards/altera/de1/syn/quartus/tcl/settings.tcl | 1 + 132 files changed, 106128 insertions(+), 0 deletions(-) create mode 100644 boards/altera/de1/Makefile.inc create mode 100644 boards/altera/de1/README create mode 100644 boards/altera/de1/backend/rtl/verilog/pll.v create mode 100644 boards/altera/de1/bench/verilog/include/eth_stim.v create mode 100644 boards/altera/de1/bench/verilog/include/orpsoc-testbench-defines.v create mode 100644 boards/altera/de1/bench/verilog/include/synthesis-defines.v create mode 100644 boards/altera/de1/bench/verilog/include/timescale.v create mode 100644 boards/altera/de1/bench/verilog/orpsoc_testbench.v create mode 100644 boards/altera/de1/bench/verilog/spi_slave.v create mode 100644 boards/altera/de1/rtl/verilog/adv_debugsys/adbg_crc32.v create mode 100644 boards/altera/de1/rtl/verilog/adv_debugsys/adbg_jsp_biu.v create mode 100644 boards/altera/de1/rtl/verilog/adv_debugsys/adbg_jsp_module.v create mode 100644 boards/altera/de1/rtl/verilog/adv_debugsys/adbg_or1k_biu.v create mode 100644 boards/altera/de1/rtl/verilog/adv_debugsys/adbg_or1k_module.v create mode 100644 boards/altera/de1/rtl/verilog/adv_debugsys/adbg_or1k_status_reg.v create mode 100644 boards/altera/de1/rtl/verilog/adv_debugsys/adbg_wb_biu.v create mode 100644 boards/altera/de1/rtl/verilog/adv_debugsys/adbg_wb_module.v create mode 100644 boards/altera/de1/rtl/verilog/adv_debugsys/adv_dbg_if.v create mode 100644 boards/altera/de1/rtl/verilog/adv_debugsys/bytefifo.v create mode 100644 boards/altera/de1/rtl/verilog/adv_debugsys/syncflop.v create mode 100644 boards/altera/de1/rtl/verilog/adv_debugsys/syncreg.v create mode 100644 boards/altera/de1/rtl/verilog/arbiter/README create mode 100644 boards/altera/de1/rtl/verilog/arbiter/arbiter_bytebus.v create mode 100644 boards/altera/de1/rtl/verilog/arbiter/arbiter_dbus.v create mode 100644 boards/altera/de1/rtl/verilog/arbiter/arbiter_ibus.v create mode 100644 boards/altera/de1/rtl/verilog/clkgen/clkgen.v create mode 100644 boards/altera/de1/rtl/verilog/flashrom/README create mode 100644 boards/altera/de1/rtl/verilog/flashrom/flashrom.v create mode 100644 boards/altera/de1/rtl/verilog/gpio/README create mode 100644 boards/altera/de1/rtl/verilog/gpio/gpio.v create mode 100644 boards/altera/de1/rtl/verilog/include/adbg_defines.v create mode 100644 boards/altera/de1/rtl/verilog/include/adbg_or1k_defines.v create mode 100644 boards/altera/de1/rtl/verilog/include/adbg_wb_defines.v create mode 100644 boards/altera/de1/rtl/verilog/include/dbg_cpu_defines.v create mode 100644 boards/altera/de1/rtl/verilog/include/dbg_defines.v create mode 100644 boards/altera/de1/rtl/verilog/include/dbg_wb_defines.v create mode 100644 boards/altera/de1/rtl/verilog/include/ethmac_defines.v create mode 100644 boards/altera/de1/rtl/verilog/include/i2c_master_slave_defines.v create mode 100644 boards/altera/de1/rtl/verilog/include/or1200_defines.v create mode 100644 boards/altera/de1/rtl/verilog/include/orpsoc-defines.v create mode 100644 boards/altera/de1/rtl/verilog/include/orpsoc-params.v create mode 100644 boards/altera/de1/rtl/verilog/include/sd_defines.v create mode 100644 boards/altera/de1/rtl/verilog/include/tap_defines.v create mode 100644 boards/altera/de1/rtl/verilog/include/uart_defines.v create mode 100644 boards/altera/de1/rtl/verilog/include/usbhostslave_constants_h.v create mode 100644 boards/altera/de1/rtl/verilog/include/usbhostslave_hostcontrol_h.v create mode 100644 boards/altera/de1/rtl/verilog/include/usbhostslave_hostslave_h.v create mode 100644 boards/altera/de1/rtl/verilog/include/usbhostslave_serialinterfaceengine_h.v create mode 100644 boards/altera/de1/rtl/verilog/include/usbhostslave_slavecontrol_h.v create mode 100644 boards/altera/de1/rtl/verilog/include/usbhostslave_wishbonebus_h.v create mode 100644 boards/altera/de1/rtl/verilog/orpsoc_top/orpsoc_top.v create mode 100644 boards/altera/de1/rtl/verilog/sdc_controller/sd_bd.v create mode 100644 boards/altera/de1/rtl/verilog/sdc_controller/sd_clock_divider.v create mode 100644 boards/altera/de1/rtl/verilog/sdc_controller/sd_cmd_master.v create mode 100644 boards/altera/de1/rtl/verilog/sdc_controller/sd_cmd_serial_host.v create mode 100644 boards/altera/de1/rtl/verilog/sdc_controller/sd_controller_wb.v create mode 100644 boards/altera/de1/rtl/verilog/sdc_controller/sd_crc_16.v create mode 100644 boards/altera/de1/rtl/verilog/sdc_controller/sd_crc_7.v create mode 100644 boards/altera/de1/rtl/verilog/sdc_controller/sd_data_master.v create mode 100644 boards/altera/de1/rtl/verilog/sdc_controller/sd_data_serial_host.v create mode 100644 boards/altera/de1/rtl/verilog/sdc_controller/sd_fifo_rx_filler.v create mode 100644 boards/altera/de1/rtl/verilog/sdc_controller/sd_fifo_tx_filler.v create mode 100644 boards/altera/de1/rtl/verilog/sdc_controller/sd_rx_fifo.v create mode 100644 boards/altera/de1/rtl/verilog/sdc_controller/sd_rx_fifo_tb.v create mode 100644 boards/altera/de1/rtl/verilog/sdc_controller/sd_tx_fifo.v create mode 100644 boards/altera/de1/rtl/verilog/sdc_controller/sdc_controller.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/Makefile create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/README create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/Makefile create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/async_fifo_mq.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/burst_length_counter_defines.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/cke_delay_counter_defines.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/codec.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/copyright.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/ctrl_counter_defines.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/dcm_pll.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/ddr_16.fzm create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/ddr_16_defines.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/ddr_ff.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/delay.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/dff_sr.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/egress_fifo.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/fifo.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/fifo_adr_counter_defines.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/fifo_fill.fzm create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/fizzim.pl create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/fsm_sdr_16.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/fsm_wb.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/gray_counter.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/inc_adr.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/latency_counter_defines.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/pre_delay_counter_defines.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/ref_counter.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/ref_counter_defines.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/ref_delay_counter_defines.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/sdr_16.fzm create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/sdr_16_defines.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_counter.xls create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_fifo_async_cmp.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_fifo_dual_port_ram_dc_sw.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_mem_ctrl_ddr.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_mem_ctrl_defines.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_mem_ctrl_ip.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_mem_ctrl_top.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_mem_ctrl_wb.v create mode 100644 boards/altera/de1/rtl/verilog/versatile_mem_ctrl/versatile_mem_ctrl.v create mode 100644 boards/altera/de1/rtl/vhdl/adv_debugsys/altera_virtual_jtag.vhd create mode 100644 boards/altera/de1/sim/bin/Makefile create mode 100644 boards/altera/de1/sim/run/Makefile create mode 100644 boards/altera/de1/sw/Makefile.inc create mode 100644 boards/altera/de1/sw/board/include/board.h create mode 100644 boards/altera/de1/sw/bootrom/Makefile create mode 100644 boards/altera/de1/sw/drivers/usbhostslave/Makefile create mode 100644 boards/altera/de1/sw/drivers/usbhostslave/include/usbhostslave-host.h create mode 100644 boards/altera/de1/sw/drivers/usbhostslave/include/usbhostslave-slave.h create mode 100644 boards/altera/de1/sw/drivers/usbhostslave/usbhostslave-host.c create mode 100644 boards/altera/de1/sw/drivers/usbhostslave/usbhostslave-slave.c create mode 100644 boards/altera/de1/sw/tests/i2c_master_slave/sim/Makefile create mode 100644 boards/altera/de1/sw/tests/i2c_master_slave/sim/i2c_master_slave-loopback.c create mode 100644 boards/altera/de1/sw/tests/usbhostslave/sim/Makefile create mode 100644 boards/altera/de1/sw/tests/usbhostslave/sim/usbhostslave-hostsimple.c create mode 100644 boards/altera/de1/sw/tests/usbhostslave/sim/usbhostslave-slavesimple.c create mode 100644 boards/altera/de1/syn/quartus/bin/Makefile create mode 100644 boards/altera/de1/syn/quartus/run/Makefile create mode 100644 boards/altera/de1/syn/quartus/sdc/JTAG_DEBUG.sdc create mode 100644 boards/altera/de1/syn/quartus/sdc/common.sdc create mode 100644 boards/altera/de1/syn/quartus/tcl/GENERIC_JTAG_TAP_pin_assignments.tcl create mode 100644 boards/altera/de1/syn/quartus/tcl/GPIO0_pin_assignments.tcl create mode 100644 boards/altera/de1/syn/quartus/tcl/UART0_pin_assignments.tcl create mode 100644 boards/altera/de1/syn/quartus/tcl/VERSATILE_SDRAM_pin_assignments.tcl create mode 100644 boards/altera/de1/syn/quartus/tcl/common_pin_assignments.tcl create mode 100644 boards/altera/de1/syn/quartus/tcl/settings.tcl _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
