>From my experiences with hardware that can handle illegal instruction exceptions occuring every 3 instructions:
epcr <= ex_dslot ? wb_pc : delayed_ex_dslot ? dl_pc : ex_pc; ---Matthew Hicks On Sat, May 19, 2012 at 2:13 PM, Julius Baxter <[email protected]> wrote: > On Sat, May 19, 2012 at 8:08 PM, Julius Baxter <[email protected]> wrote: >> On Mon, Apr 30, 2012 at 7:31 PM, R. Diez <[email protected]> wrote: >>> Hi all: >>> >>> I'm having fun once again while running my modified test suite against the >>> CPU bundled with ORPSoC V2. >>> >>> I'm testing the range exception with this pseudo-instruction: >>> >>> l.add, 0x40000000, 0x40000000 >>> >>> That translates to the following instruction: >>> >>> 3080: e0 85 30 00 l.add r4, r5, r6 >>> >>> Given the values in the R5 and R6 at that point in time, the instruction >>> sets the overflow flag, and, because the SPR_SR_OVE flag is also set, it >>> generates a range exception. >>> >>> I added an l.nop trace inside the corresponding exception handler, and >>> or1ksim sets SPR_EPCR_BASE correctly with the address of the offending >>> instruction (3080). However, the Icarus Verilog simulation of the or1200 >>> core bundled with ORPSoC V2 sets SPR_EPCR_BASE to the next address (3084). >>> That's not right, is it? >>> >>> Anyway, the exception handler patches the offending exception, replacing it >>> with an "l.nop 0", and or1ksim continues the test suite execution without >>> problems with instruction l.rfe (Return From Exception). However, the ORPSoC >>> simulation does not, it enters an infinite range exception loop at that >>> address (3084). >> >> I can confirm that I see the incorrect PC value ending up in the EPCR >> register. It's 4 greater than it should be. This is a bug. >> > > Setting the PC to take on exception from the decode stage to the > exception stage appears to fix the problem in the case you've > mentioned. More testing should be done to check it in the delay slot: > > Index: rtl/verilog/or1200/or1200_except.v > =================================================================== > --- rtl/verilog/or1200/or1200_except.v (revision 798) > +++ rtl/verilog/or1200/or1200_except.v (working copy) > > @@ -572,25 +586,29 @@ > epcr <= ex_dslot ? > wb_pc : delayed1_ex_dslot ? > id_pc : delayed2_ex_dslot ? > - id_pc : id_pc; > + id_pc : ex_pc; > _______________________________________________ > OpenRISC mailing list > [email protected] > http://lists.openrisc.net/listinfo/openrisc _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
