On Tue, 2012-05-29 at 21:38 +0300, Stefan Kristiansson wrote:
> On 05/29/2012 09:26 PM, R. Diez wrote:
> > Hallo Julius:
> >
> > The jump instruction l.jalr is not triggering the illegal instruction
> > exception when the target register is the link register (R9). I've tested
> > it
> > with my modified test suite against ORPSoC V2's copy of the or1200 core.
> > When
> > running under the or1ksim simulator, the exception is correctly triggered.
> >
>
> I don't think it is defined anywhere that l.jalr r9 should cause an
> illegal instruction exception, so in theory it is or1ksim that is behaving
> incorrectly.
The description of l.jalr in the architecture manual says:
The contents of general-purpose register rB is the effective
address of the jump. The program unconditionally jumps to EA
with a delay of one instruction. The address of the instruction
after the delay slot is placed in the link register. It is not
allowed to specify link register as rB.
The manual doesn't say what should happen if you do specify the link
register as rB. In particular it says this instruction does not generate
exceptions. But if it isn't allowed, an exception seems a reasonable
response (the alternative being that the jump address is undefined, so
may go anywhere).
Why you can't use the link register is another matter. I presume due to
the difficulty of exception handling in the delay slot.
Either way we need a patch to the architecture manual to make things
clear.
Jeremy
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