hi,
I'm doing the orpsoc project on the xilinx ml501 board and i have installed
the software.I have 'make rtl-tests' successfully from the
path"orpsocv2/sim/run",but i'm in trouble when i 'make rtl-test' on the
path"orpsocv2/boards/xilinx/ml501/sim/run".
I download the source from svn and make some adjustment:
[1] uncomment 'define CFI_FLASH' in the orpsoc_defines.v
[2] uncomment 'Boot from 0xf0000100' and comment the others in the
or1200_defines.v;
[3] have cfi-flash.vmem file into the board's sim/run path;
[4] have" #ifndef PRELOAD_RAM
#define BOOTROM_SPI_FLASH
#else
#define BOOTROM_GOTO_RESET
#endif" in the board's board.h file;
I can't get the expected results and the result appears in the attachment.
I have this problem several days and no progress,what can i do?
Look forward to your help and extremely grateful to your help!
Regards,
Mr zsc
root@zsc-desktop:~/orpsocv2/boards/xilinx/ml501/sim/run# make rtl-test
ls: cannot access
/root/orpsocv2/boards/xilinx/ml501/sim/run/../../backend/rtl/verilog/*.v: No
such file or directory
### Compiling software ###
make[1]: Entering directory `/root/orpsocv2/sw/tests/or1200/sim'
make[2]: Entering directory `/root/orpsocv2/sw/drivers/or1200'
### Creating software defines header from verilog defines ###
### Creating OR1200 software defines header from verilog defines ###
make[2]:Leaving directory `/root/orpsocv2/sw/drivers/or1200'
### Building software support library ###
make[2]: Entering directory `/root/orpsocv2/sw/lib'
make[3]: Entering directory `/root/orpsocv2/sw/drivers/cfi-ctrl'
make[3]:Leaving directory `/root/orpsocv2/sw/drivers/cfi-ctrl'
make[3]: Entering directory `/root/orpsocv2/sw/drivers/ethmac'
make[3]:Leaving directory `/root/orpsocv2/sw/drivers/ethmac'
make[3]: Entering directory `/root/orpsocv2/sw/drivers/i2c_master_slave'
make[3]:Leaving directory `/root/orpsocv2/sw/drivers/i2c_master_slave'
make[3]: Entering directory `/root/orpsocv2/sw/drivers/or1200'
make[3]:Leaving directory `/root/orpsocv2/sw/drivers/or1200'
make[3]: Entering directory `/root/orpsocv2/sw/drivers/simple-spi'
make[3]:Leaving directory `/root/orpsocv2/sw/drivers/simple-spi'
make[3]: Entering directory `/root/orpsocv2/sw/drivers/uart'
make[3]:Leaving directory `/root/orpsocv2/sw/drivers/uart'
make[2]:Leaving directory `/root/orpsocv2/sw/lib'
rm or1200-simple.bin or1200-simple.elf
make[1]:Leaving directory `/root/orpsocv2/sw/tests/or1200/sim'
### Generating bootup ROM ###
make[1]: Entering directory `/root/orpsocv2/boards/xilinx/ml501/sw/bootrom'
make[2]: Entering directory `/root/orpsocv2/sw/bootrom'
rm bootrom.o bootrom.bin
make[2]:Leaving directory `/root/orpsocv2/sw/bootrom'
â../../../../../sw/bootrom/bootrom.vâ -> â./bootrom.vâ
make[1]:Leaving directory `/root/orpsocv2/boards/xilinx/ml501/sw/bootrom'
### Compiling Verilog design library ###
** Warning: (vlog-2103) Directory
"/root/orpsocv2/boards/xilinx/ml501/sim/run/../../backend/rtl/verilog" for -y
option not found.
### Compiling Xilinx support libs, user design & testbench ###
** Warning:
/root/orpsocv2/boards/xilinx/ml501/sim/run/../../../../../bench/verilog/include/cfi_flash_TimingData.h(195):
(vopt-2250) Function "getTime" has no return value assignment.
### Launching simulation ###
Reading /opt/modelsim/modeltech/tcl/vsim/pref.tcl
# 6.6
# vsim -do {set StdArithNoWarnings 1; run -all; exit} -c -quiet -suppress 8598
tb
# set StdArithNoWarnings 1
# 1
# run -all
# Block Memory Generator CORE Generator module
orpsoc_testbench.dut.xilinx_ddr2_0.xilinx_ddr2_if0.cache_mem0.inst is using a
behavioral model for simulation which will not precisely model memory collision
behavior.
# Xilinx DDR2 MIGed controller at
orpsoc_testbench.dut.xilinx_ddr2_0.xilinx_ddr2_if0.ddr2_mig0
#
#
# * Starting simulation of design RTL.
# * Test: or1200-simple
#
# [ 0 ns] --- Device is Busy (start up time) ---
# [ 0 ns] ASynchronous Read Mode
# [ 0 ns] VDDQ Voltage is OK
# [ 0 ns] VDD Voltage is OK
# [ 0 ns] Inizialize the Memory to default value
# [ 0 ns] Load Memory from file: cfi-flash.vmem
# (1 ns)(orpsoc_testbench.eth_phy0)PHY configured to 100 Mbps!
# (1 ns)(orpsoc_testbench.eth_phy0)Ethernet link is up!
# Input Error : RST on instance
orpsoc_testbench.dut.xilinx_ddr2_0.xilinx_ddr2_if0.ddr2_mig0.u_ddr2_infrastructure.gen_pll_adv.u_pll_adv
at time 112 ns must be asserted at least for 10 ns.
# [ 173 ns] Device has been reset
# [ 300 ns] --- Device is Ready (end of start-up time) ---
# [ 638 ns] Data Read result: memory[000080]=1800
# [ 639 ns] Data Read result: memory[000080]=1800
# [ 743 ns] Data Read result: memory[000081]=0000
# [ 938 ns] Data Read result: memory[000082]=1820
# [ 939 ns] Data Read result: memory[000082]=1820
# [ 1043 ns] Data Read result: memory[000083]=0000
# [ 1238 ns] Data Read result: memory[000084]=1840
# [ 1239 ns] Data Read result: memory[000084]=1840
# [ 1343 ns] Data Read result: memory[000085]=0000
# [ 1538 ns] Data Read result: memory[000086]=1860
# [ 1539 ns] Data Read result: memory[000086]=1860
# [ 1643 ns] Data Read result: memory[000087]=0000
# [ 1838 ns] Data Read result: memory[000088]=1880
# [ 1839 ns] Data Read result: memory[000088]=1880
# [ 1943 ns] Data Read result: memory[000089]=0000
# [ 2138 ns] Data Read result: memory[00008a]=18a0
# [ 2139 ns] Data Read result: memory[00008a]=18a0
# [ 2243 ns] Data Read result: memory[00008b]=0000
# [ 2438 ns] Data Read result: memory[00008c]=18c0
# [ 2439 ns] Data Read result: memory[00008c]=18c0
# [ 2543 ns] Data Read result: memory[00008d]=0000
# [ 2738 ns] Data Read result: memory[00008e]=18e0
# [ 2739 ns] Data Read result: memory[00008e]=18e0
# [ 2843 ns] Data Read result: memory[00008f]=0000
# [ 3038 ns] Data Read result: memory[000090]=1900
# [ 3039 ns] Data Read result: memory[000090]=1900
# [ 3143 ns] Data Read result: memory[000091]=0000
# [ 3338 ns] Data Read result: memory[000092]=1920
# [ 3339 ns] Data Read result: memory[000092]=1920
# [ 3443 ns] Data Read result: memory[000093]=0000
# [ 3638 ns] Data Read result: memory[000094]=1940
# [ 3639 ns] Data Read result: memory[000094]=1940
# [ 3743 ns] Data Read result: memory[000095]=0000
# [ 3938 ns] Data Read result: memory[000096]=1960
# [ 3939 ns] Data Read result: memory[000096]=1960
# [ 4043 ns] Data Read result: memory[000097]=0000
# [ 4238 ns] Data Read result: memory[000098]=1980
# [ 4239 ns] Data Read result: memory[000098]=1980
# [ 4343 ns] Data Read result: memory[000099]=0000
# [ 4538 ns] Data Read result: memory[00009a]=19a0
# [ 4539 ns] Data Read result: memory[00009a]=19a0
# [ 4643 ns] Data Read result: memory[00009b]=0000
# [ 4838 ns] Data Read result: memory[00009c]=19c0
# [ 4839 ns] Data Read result: memory[00009c]=19c0
# [ 4943 ns] Data Read result: memory[00009d]=0000
# [ 5138 ns] Data Read result: memory[00009e]=19e0
# [ 5139 ns] Data Read result: memory[00009e]=19e0
# [ 5243 ns] Data Read result: memory[00009f]=0000
# [ 5438 ns] Data Read result: memory[0000a0]=1a00
# [ 5439 ns] Data Read result: memory[0000a0]=1a00
# [ 5543 ns] Data Read result: memory[0000a1]=0000
# [ 5738 ns] Data Read result: memory[0000a2]=1a20
# [ 5739 ns] Data Read result: memory[0000a2]=1a20
# [ 5843 ns] Data Read result: memory[0000a3]=0000
# [ 6038 ns] Data Read result: memory[0000a4]=1a40
# [ 6039 ns] Data Read result: memory[0000a4]=1a40
# [ 6143 ns] Data Read result: memory[0000a5]=0000
# [ 6338 ns] Data Read result: memory[0000a6]=1a60
# [ 6339 ns] Data Read result: memory[0000a6]=1a60
# [ 6443 ns] Data Read result: memory[0000a7]=0000
# [ 6638 ns] Data Read result: memory[0000a8]=1a80
# [ 6639 ns] Data Read result: memory[0000a8]=1a80
# [ 6743 ns] Data Read result: memory[0000a9]=0000
# [ 6938 ns] Data Read result: memory[0000aa]=1aa0
# [ 6939 ns] Data Read result: memory[0000aa]=1aa0
# [ 7043 ns] Data Read result: memory[0000ab]=0000
# [ 7238 ns] Data Read result: memory[0000ac]=1ac0
# [ 7239 ns] Data Read result: memory[0000ac]=1ac0
# [ 7343 ns] Data Read result: memory[0000ad]=0000
# [ 7538 ns] Data Read result: memory[0000ae]=1ae0
# [ 7539 ns] Data Read result: memory[0000ae]=1ae0
# [ 7643 ns] Data Read result: memory[0000af]=0000
# [ 7838 ns] Data Read result: memory[0000b0]=1b00
# [ 7839 ns] Data Read result: memory[0000b0]=1b00
# [ 7943 ns] Data Read result: memory[0000b1]=0000
# [ 8138 ns] Data Read result: memory[0000b2]=1b20
# [ 8139 ns] Data Read result: memory[0000b2]=1b20
# [ 8243 ns] Data Read result: memory[0000b3]=0000
# [ 8438 ns] Data Read result: memory[0000b4]=1b40
# [ 8439 ns] Data Read result: memory[0000b4]=1b40
# orpsoc_testbench.gen_cs[0].gen[0].u_mem0.cmd_task: at time 8526 ns
WARNING: 200 us is required before CKE goes active.
# orpsoc_testbench.gen_cs[0].gen[1].u_mem0.cmd_task: at time 8526 ns
WARNING: 200 us is required before CKE goes active.
# orpsoc_testbench.gen_cs[0].gen[2].u_mem0.cmd_task: at time 8526 ns
WARNING: 200 us is required before CKE goes active.
# orpsoc_testbench.gen_cs[0].gen[3].u_mem0.cmd_task: at time 8526 ns
WARNING: 200 us is required before CKE goes active.
# [ 8543 ns] Data Read result: memory[0000b5]=0000
# [ 8738 ns] Data Read result: memory[0000b6]=1b60
# [ 8739 ns] Data Read result: memory[0000b6]=1b60
# [ 8843 ns] Data Read result: memory[0000b7]=0000
# [ 9038 ns] Data Read result: memory[0000b8]=1b80
# [ 9039 ns] Data Read result: memory[0000b8]=1b80
# [ 9143 ns] Data Read result: memory[0000b9]=0000
# [ 9338 ns] Data Read result: memory[0000ba]=1ba0
# [ 9339 ns] Data Read result: memory[0000ba]=1ba0
# [ 9443 ns] Data Read result: memory[0000bb]=0000
# [ 9638 ns] Data Read result: memory[0000bc]=1bc0
# [ 9639 ns] Data Read result: memory[0000bc]=1bc0
# [ 9743 ns] Data Read result: memory[0000bd]=0000
# [ 9938 ns] Data Read result: memory[0000be]=1be0
# [ 9939 ns] Data Read result: memory[0000be]=1be0
# [ 10043 ns] Data Read result: memory[0000bf]=0000
# [ 10238 ns] Data Read result: memory[0000c0]=a820
# [ 10239 ns] Data Read result: memory[0000c0]=a820
# [ 10343 ns] Data Read result: memory[0000c1]=0001
# [ 10538 ns] Data Read result: memory[0000c2]=c000
# [ 10539 ns] Data Read result: memory[0000c2]=c000
# [ 10643 ns] Data Read result: memory[0000c3]=0811
# [ 10838 ns] Data Read result: memory[0000c4]=c140
# [ 10839 ns] Data Read result: memory[0000c4]=c140
# [ 10943 ns] Data Read result: memory[0000c5]=0000
# [ 11138 ns] Data Read result: memory[0000c6]=1880
# [ 11139 ns] Data Read result: memory[0000c6]=1880
# [ 11243 ns] Data Read result: memory[0000c7]=0000
# [ 11438 ns] Data Read result: memory[0000c8]=a884
# [ 11439 ns] Data Read result: memory[0000c8]=a884
# [ 11543 ns] Data Read result: memory[0000c9]=2028
# [ 11738 ns] Data Read result: memory[0000ca]=4400
# [ 11739 ns] Data Read result: memory[0000ca]=4400
# [ 11843 ns] Data Read result: memory[0000cb]=2000
# [ 12038 ns] Data Read result: memory[0000cc]=1500
# [ 12039 ns] Data Read result: memory[0000cc]=1500
# [ 12143 ns] Data Read result: memory[0000cd]=0000
# First Stage Calibration completed at time 25988 ns
# Second Stage Calibration completed at time 32918 ns
# Third Stage Calibration completed at time 40320 ns
# Fourth Stage Calibration completed at time 51338 ns
# Calibration completed at time 51338 ns
^C# ** Fatal: (SIGSEGV) Bad handle or reference.
# Time: 227806975 ps Iteration: 3 Process:
/orpsoc_testbench/gen_cs[0]/gen[2]/u_mem0/#ALWAYS#1346(main) File:
/root/orpsocv2/boards/xilinx/ml501/sim/run/../../bench/verilog/ddr2_model.v
# Fatal error at
/root/orpsocv2/boards/xilinx/ml501/sim/run/../../bench/verilog/ddr2_model.v
line 1476
#
# HDL call sequence:
# Stopped at
/root/orpsocv2/boards/xilinx/ml501/sim/run/../../bench/verilog/ddr2_model.v
1476
#
# exit
make: *** [modelsim] Interrupt
root@zsc-desktop: ~/orpsocv2_______________________________________________
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