Hi I've finally put up the processor core I've been playing with over the last little while.
https://github.com/openrisc/mor1kx Documentation is a bit lacking, so too is the verification environment which I hope to release sometime soon. Special thanks to Stefan Kristiansson who helped out with testing and developed the caches. Some quick facts: * It has two pipeline implementations, a 4 stage single issue version which is tightly coupled with the caches, called "cappuccino". The other is a 2 stage single issue pipeline dubbed "espresso" which doesn't have caches (although can burst over Wishbone). * It's configured by parameters - not a single `define controlling implementation * No MMU * ORBIS32 support only, so no floating point or vector instructions, but hardware divide and multiply supported. * Both pipelines support delay slot (a version of espresso without is in the works) * Both have PIC, TT and debug units I don't have any implementation details at hand, perhaps Stefan can dig out some, but it's at least on par with the OR1200, if not better in some respects regarding area and maximum frequency. This is not an official release, just an announcement that it's now publicly available. Testers welcome and encouraged :) I've licensed it under the OHDL thing I came up with (a Mozilla Public License 2 derivative) but the license states you're welcome to relicense it under something less permissive like a GNU one or the TAPR/CERN open hardware licenses. Cheers Jules _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
