On Tue, Sep 25, 2012 at 12:28 AM, Yann Vernier <[email protected]> wrote: > The thread http://opencores.org/forum,OpenRISC,0,5005 about GDB failing > to single-step after certain breakpoints led us to a logic error in the > debug unit. When the pipeline is stalled for other reasons, for > instance an instruction fetch (therefore affected by instruction > cache), at the cycle _after_ a trap instruction is decoded, the trap > signal is never lowered since no new instruction is decoded. This locks > the debug unit into stalling continuously.
Hi Yann, Sounds like good work on tracking this down. Can this be recreated in simulation via the JTAG-via-VPI interface? I'm not saying you need to, but it would be good to know that this bug is fixed by observing it in simulation, and/or having a regression test which, or instructions how to, trigger this bug. How did you work this out this is the right fix? > > Attached is a workaround to make the debug unit aware that the sig_trap > and sig_syscall signals only update when the ex stage is not stalled. > This fixes the issue we've observed, although similar conditions may > exist for any other exceptions. Also note that the debug interface uses > a priority encoder to only catch one of the events that occur; > short-lived events may therefore be ignored completely. Can you elaborate on this? Which "short-lived events" are you talking about? > > Any comments? Personally I feel it's a bit of a stopgap measure, > addressing this problem narrowly, but it's better than the current > state. Can you please post the patch inline? Thanks again! Julius _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
