On Tue, Oct 2, 2012 at 5:18 AM, R. Diez <[email protected]> wrote:
> According to the rules above, the Overflow flag should be True, which is 
> wrong,
> regardless of which top bits I choose to look at (the highest 32 or 33).

Yeah, you're right.  I guess I wrote that in a bit of a hurry.

Anyway, what I meant by a standard multiplier was essentially this:

entity mul is
  generic (bits : integer);
  port (mulsigned : in std_logic; src1, src2 : in
std_logic_vector(bits-1 downto 0); result : out
std_logic_vector(2*bits-1 downto 0));
end;

Most of the hard macro multipliers I've seen are something like this.

So for l.mul, you set signed to '1', and use the logic I described
earlier.  For l.mulu, you set signed to '0'.

Then we could add 2 opcodes, l.mulf and l.muluf (for multiply-full &
multiply-unsigned-full) that dump their results in the HI and LO
registers.

That sort of multiplier is hard to code in VHDL (and Verilog) in a way
that you can be confident it will be inferred correctly.  You can
almost do it like this:

architecture rtl of mul is
  comb : process (mulsigned, src1, src2) is
  begin
    if mulsigned = '1' then
      result <= signed(src1) * signed(src2);
    else
      result <= unsigned(src1) * unsigned(src2);
    end if;
  end;
end;

You just have to hope the synthesizer doesn't infer two multipliers,
which isn't a completely unreasonable hope, since they'll often infer
a single adder for something like this:

comb : process (sub, src1, src2) is
  if sub = '0' then
    result <= src1 + src2;
  else
    result <= src1 - src2;
  end if;
end;

You can also try inferring it like this:

comb : process (mulsigned, src1, src2) is
  variable t1, t2 : std_logic_vector(bits downto 0);
begin
  -- forced unsigned multiply using signed multiplier by appending a
sign bit at the top
  t1 := (mulsigned and src1(bits-1)) & src1;
  t2 := (mulsigned and src2(bits-1)) & src2;
  result <= signed(t1) * signed(t2);
end;

But you might get a 33x33->66 multiplier like that.  You also can try
this method if your multiplier doesn't have a 'signed' input port.

Keep in mind if you can't make your synthesizer infer it correctly,
you can just instantiate the macro yourself :)

-Pete
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