> Thanks for spotting that, indeed, the reset vector routine does not set > R0 to zero. I will correct that. All other issues are more than > welcomed! If you can send them before the weekend we can mention them on > the project meeting.
Good, let's start with redboot_linux_exec.c . I've rewritten the "asm volatile" section so that it's compatible with CPUs with and without jump delay slots, please see the attached file. I hope you don't mind the small performance loss. I've added some comments and done some reformatting in order to make the code easier to understand. I haven't managed to make Redboot work yet, so I think you should review any changes carefully and maybe test them locally. Other than that, I've only made changes to vectors.S , I didn't see any other hand-writen assembly code that used jump delay slots. I'll post about that later on in a separate e-mail. > I think we could add a configuration option for eCos to build code > without delay slots. Diffs describing your modifications will help a lot > if you could be so kind and share them. I'm going to need some help here. I believe there is no easy way to set eCos configuration options from the command line, or is there? I'm building eCos automatically (with a build script that starts from scratch, downloading a fresh source repository). I could generate a default configuration file and then patch it, but maintaining such patches is pain. Is there a way to pass CFLAGS from outside, or do they get overwritten by CYGBLD_GLOBAL_CFLAGS? I need to use Peter Gavin's toolchain with -mcompat-delay . I also had to modify packages/hal/openrisc/orpsoc/current/cdl/hal_openrisc_orpsoc.cdl , CYGBLD_GLOBAL_COMMAND_PREFIX, as Peter Gavin's toolchain uses "or1k-elf" instead of "or32-elf". Thanks, rdiez
trampoline(base_addr, base_addr + length, target, entry); // We never reach this point. The code below gets copied beforehand to some other memory address, // is run at that destination address and never returns. asm volatile ( // All code below must be position independent, as it will run on another memory address. "__tramp_start__: \n" // R3 is base_addr // R4 is base_addr + length // R5 is target // R6 is the entry point to jump to at the end // The loop below is a kind of memcpy(), it copies all program data from the base address to the target address. // All jump delay slots are empty in order to be compatible with CPUs with and without such slots. // If you need to optimise the copying, consider unwinding the loop or at least checking the loop condition // at the end (in order to have just one jump instruction per iteration). "1: l.sfeq r3, r4 \n" " l.bf 2f \n" " l.nop # Empty jump delay slot. \n" " l.lwz r13, 0x00(r3) \n" " l.sw 0x00(r5), r13 \n" " l.addi r3, r3, 4 \n" " l.addi r5, r5, 4 \n" " l.j 1b \n" " l.nop # Empty jump delay slot. \n" // Jump to the entry point, which never returns. "2: l.jr r6 \n" " l.nop # Empty jump delay slot. \n" "__tramp_end__: \n" : /* no output registers */ : /* no input registers */ : /* no clobbered registers */ );
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