We had some questions on the GNU compiler during this weekend's meeting, which I put to Joern Rennecke (who implemented the 4.5.1 compiler). Here are his replies:
Q1 Are rotate instructions ever generated by GCC? A1 gcc recognizes a combination of right+left shift tied with addition Q2 Are sign extension instructions useful? A2 sign and zero extensions are useful for certain codes, which includes some EEMBC benchmarks. Although some uses cases could be addressed even better if you had actual byte / short word arithmetic. But that'd not be RISC. The common strategy to synthesize sign extensions if they are not provided with a instruction pattern is to use a left shift & arithmetic right shift. Of course, that's two at least instructions, and if the processor has no barrel shifter and / or pipeline issues with shifts, this can get really expensive. Q3 Can CGEN now handle mixed 16- and 32-bit instructions. There was a post in 2002, suggesting this was a problem for ARC. A3 When I last worked on cgen for ARCompact (2008?), there were still issues with mixed 16/32 bit code. I did some hackery to work around them. HTH, Jeremy -- Tel: +44 (1590) 610184 Cell: +44 (7970) 676050 SkypeID: jeremybennett Email: [email protected] Web: www.embecosm.com _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
