Hallo Peter: >Ok, I'm interested to see how you get both flags from one multiplier. > [...] > My two biggest concerns are that I don't know why one > would care about unsigned overflow when doing signed multiply, > and it's not really easy to implement, especially if you want > to use FPGA DSP slices.
Yes, that's the reason I started the previous discussion thread about the multiplication instructions. What I mean is that, in my implementation, the unsigned multiplication instruction sets CY if necessary for unsigned overflow, and the signed multiplication instructions set OV if necessary for signed overflow. Unsigned multiplication only calculates unsigned overflow, and signed multiplication only calculates signed overflow. Look at my previous e-mails for more details about how the or1ksim implementation differs, and why a single 32x32 multiplier is probably worse than a single 33x33 one. Take a look at OR10's Verilog source code to see how I've implemented both multiplication types with a single 33x33->66 bit signed hardware multiplier. Xilinx' XST chains 4 DSP48A1s together. The OR10 readme file has also more information on this. Have you considered adding a separate trap for the CY flag instead, like I mentioned in my last e-mail? That could benefit other arithmetic instructions too, and would probably be less of an impact on existing software. >l.mulf, l.mulfu: do a full signed/unsigned 32x32-to-64 bit multiply, storing >results to MACLO/HI The 'f' suffix might may programmers think about floating point numbers. How about using 'd' for double-word, 'q' for quad, or something else? Regards, rdiez _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
