--- .../rtl/verilog/include/or1200_defines.v | 1 + .../atlys/rtl/verilog/include/or1200_defines.v | 1 + .../ml501/rtl/verilog/include/or1200_defines.v | 1 + .../rtl/verilog/include/or1200_defines.v | 1 + 4 files changed, 4 insertions(+)
diff --git a/boards/actel/ordb1a3pe1500/rtl/verilog/include/or1200_defines.v b/boards/actel/ordb1a3pe1500/rtl/verilog/include/or1200_defines.v index b5b29bf..3d4659f 100644 --- a/boards/actel/ordb1a3pe1500/rtl/verilog/include/or1200_defines.v +++ b/boards/actel/ordb1a3pe1500/rtl/verilog/include/or1200_defines.v @@ -699,6 +699,7 @@ `define OR1200_OR32_MACI 6'b010011 /* */ `define OR1200_OR32_LWZ 6'b100001 +`define OR1200_OR32_LWS 6'b100010 `define OR1200_OR32_LBZ 6'b100011 `define OR1200_OR32_LBS 6'b100100 `define OR1200_OR32_LHZ 6'b100101 diff --git a/boards/xilinx/atlys/rtl/verilog/include/or1200_defines.v b/boards/xilinx/atlys/rtl/verilog/include/or1200_defines.v index 4159c93..3ebcb58 100644 --- a/boards/xilinx/atlys/rtl/verilog/include/or1200_defines.v +++ b/boards/xilinx/atlys/rtl/verilog/include/or1200_defines.v @@ -698,6 +698,7 @@ `define OR1200_OR32_MACI 6'b010011 /* */ `define OR1200_OR32_LWZ 6'b100001 +`define OR1200_OR32_LWS 6'b100010 `define OR1200_OR32_LBZ 6'b100011 `define OR1200_OR32_LBS 6'b100100 `define OR1200_OR32_LHZ 6'b100101 diff --git a/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v b/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v index 28e6788..59b9184 100644 --- a/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v +++ b/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v @@ -698,6 +698,7 @@ `define OR1200_OR32_MACI 6'b010011 /* */ `define OR1200_OR32_LWZ 6'b100001 +`define OR1200_OR32_LWS 6'b100010 `define OR1200_OR32_LBZ 6'b100011 `define OR1200_OR32_LBS 6'b100100 `define OR1200_OR32_LHZ 6'b100101 diff --git a/boards/xilinx/s3adsp1800/rtl/verilog/include/or1200_defines.v b/boards/xilinx/s3adsp1800/rtl/verilog/include/or1200_defines.v index 743cd12..6792abe 100644 --- a/boards/xilinx/s3adsp1800/rtl/verilog/include/or1200_defines.v +++ b/boards/xilinx/s3adsp1800/rtl/verilog/include/or1200_defines.v @@ -698,6 +698,7 @@ `define OR1200_OR32_MACI 6'b010011 /* */ `define OR1200_OR32_LWZ 6'b100001 +`define OR1200_OR32_LWS 6'b100010 `define OR1200_OR32_LBZ 6'b100011 `define OR1200_OR32_LBS 6'b100100 `define OR1200_OR32_LHZ 6'b100101 -- 1.7.9.5 _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
