This test would go into an endless loop when caches are not present.
---
sw/tests/or1200/sim/or1200-dsxinsn.S | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/sw/tests/or1200/sim/or1200-dsxinsn.S
b/sw/tests/or1200/sim/or1200-dsxinsn.S
index 7f36f91..dc3bb23 100644
--- a/sw/tests/or1200/sim/or1200-dsxinsn.S
+++ b/sw/tests/or1200/sim/or1200-dsxinsn.S
@@ -236,6 +236,13 @@ _start:
/* TODO - track and check the number of TLB misses we should
have incurred */
+ /* Check if IC present and skip enabling otherwise */
+ l.mfspr r3,r0,SPR_UPR
+ l.andi r4,r3,SPR_UPR_ICP
+ l.sfeq r4,r0
+ l.bf test_ok
+ l.nop
+
/* Now repeat the tests with caches enabled if they weren't */
l.mfspr r1,r0,SPR_SR
l.andi r1,r1,SPR_SR_ICE
--
1.7.9.5
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