On Fri, Apr 12, 2013 at 12:05 PM, Olof Kindgren <[email protected]> wrote: > From fffc028793250bd944390de599231d6d670e4326 Mon Sep 17 00:00:00 2001 > From: Olof Kindgren <[email protected]> > Date: Thu, 11 Apr 2013 14:10:11 +0200 > Subject: [PATCH] Exclude gpr accessor functions from synthesis > > Synplify pro fails when it encounters set_gpr.
First patch from neither Stefan or myself! (I think!) You join an elite club, Olof ;) > --- > rtl/verilog/mor1kx_cpu_cappuccino.v | 4 ++++ > rtl/verilog/mor1kx_cpu_espresso.v | 4 ++++ > rtl/verilog/mor1kx_cpu_prontoespresso.v | 4 ++++ > 3 files changed, 12 insertions(+), 0 deletions(-) > > diff --git a/rtl/verilog/mor1kx_cpu_cappuccino.v > b/rtl/verilog/mor1kx_cpu_cappuccino.v > index d5008d2..7c1e003 100644 > --- a/rtl/verilog/mor1kx_cpu_cappuccino.v > +++ b/rtl/verilog/mor1kx_cpu_cappuccino.v > @@ -677,6 +677,8 @@ module mor1kx_cpu_cappuccino > .pipeline_flush_i (pipeline_flush_o)); // Templated > > > +`ifndef SYNTHESIS > +// synthesis translate_off Do we need both, `ifndef and //synthesis translate_off? Otherwise this seems fine. > /* Debug signals required for the debug monitor */ > function [OPTION_OPERAND_WIDTH-1:0] get_gpr; > // verilator public > @@ -707,6 +709,8 @@ module mor1kx_cpu_cappuccino > mor1kx_rf_cappuccino.rfb.ram[gpr_num] = gpr_value; > end > endtask > +// synthesis translate_on > +`endif > > > /* mor1kx_execute_ctrl_cappuccino AUTO_TEMPLATE ( > diff --git a/rtl/verilog/mor1kx_cpu_espresso.v > b/rtl/verilog/mor1kx_cpu_espresso.v > index 149f3a1..f3754ed 100644 > --- a/rtl/verilog/mor1kx_cpu_espresso.v > +++ b/rtl/verilog/mor1kx_cpu_espresso.v > @@ -558,6 +558,8 @@ module mor1kx_cpu_espresso > end > endfunction > > +`ifndef SYNTHESIS > +// synthesis translate_off > task set_gpr; > // verilator public > input [4:0] gpr_num; > @@ -567,6 +569,8 @@ module mor1kx_cpu_espresso > mor1kx_rf_espresso.rfb.ram[gpr_num] = gpr_value; > end > endtask > +// synthesis translate_on > +`endif > > /* mor1kx_ctrl_espresso AUTO_TEMPLATE ( > .ctrl_alu_result_i (alu_result_o), > diff --git a/rtl/verilog/mor1kx_cpu_prontoespresso.v > b/rtl/verilog/mor1kx_cpu_prontoespresso.v > index a6c4d97..7ab40f8 100644 > --- a/rtl/verilog/mor1kx_cpu_prontoespresso.v > +++ b/rtl/verilog/mor1kx_cpu_prontoespresso.v > @@ -635,6 +635,8 @@ module mor1kx_cpu_prontoespresso > endfunction // > > > +`ifndef SYNTHESIS > +// synthesis translate_off > task set_gpr; > // verilator public > input [4:0] gpr_num; > @@ -644,6 +646,8 @@ module mor1kx_cpu_prontoespresso > mor1kx_rf_espresso.rfb.ram[gpr_num] = gpr_value; > end > endtask > +// synthesis translate_on > +`endif > > /* mor1kx_ctrl_prontoespresso AUTO_TEMPLATE ( > .ctrl_alu_result_i (alu_result_o), > -- > 1.7.9 > > > > _______________________________________________ > OpenRISC mailing list > [email protected] > http://lists.openrisc.net/listinfo/openrisc > _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
