On Mon, Aug 26, 2013 at 2:42 PM, Martin Schulze <[email protected]> wrote: > I stumbled over two implementations of the Wishbone Bus, one multiplexed > and one registered. I wonder if the registered bus is used and if this > distinction is important for different FPGA vendors or ASIC use.
There are a few versions of the standard. The B3 introduced registered feedback cycles, basically making bursts better in terms of implementability. If you're doing burst accesses on the wishbone bus, you'll want to do it that way, whether you're targeting FPGA or ASIC. Cheers Julius _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
