On Wed, Sep 25, 2013 at 4:36 PM, Stefan Wallentowitz < [email protected]> wrote:
> Dear All, > > I have been working around with generated buses (different number of > masters and slaves) etc. before and recently implemented a new bus that > can be much easier configured in my systems by parameters. > You can find the bus plus the arbiter module in a github repo: > wallento/wb_interconnect > > Direct link to verilog toplevel including instantiation example: > https://github.com/wallento/wb_interconnect/blob/master/wb_bus_b3.v > > Maybe this is useful to anybody. > > Bye, > Stefan > > > _______________________________________________ > OpenRISC mailing list > [email protected] > http://lists.openrisc.net/listinfo/openrisc > > Hi Stefan, This shows yet again that the need for good interconnect components is a big issue for us. I probably should have advertised this a bit better, but I developed something quite similar for orpsocv3 just a while ago. Hopefully we can learn something from each other's implementation (at least I know that I should be a bit more verbose with what I am doing :)) The code will probably be moved to a separate repo at some point in time, but it is currently hosted as a sub project in orpsoc-cores. You can find it here if you want to take a look https://github.com/openrisc/orpsoc-cores/tree/master/cores/wb_intercon Cheers, Olof
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