On Sun, Oct 6, 2013 at 10:10 PM, Peter Gavin <[email protected]> wrote:
> Ok, I've added the things already described to the wiki. > > I have a few other concerns: > > As always, you raise valid concerns that we others seem to oversee. I myself don't have any definite answers, but here's at least some input and some insight how it works in mor1kx (which doesn't necessarily mean that is the correct behavior). > The manual requires that the ESR register be initialized to zero on reset. > Some of the bits in SR are immutable, or reserved, such as the FO bit, for > example. Should it be possible to set the ESR bit in the FO position to > zero? Or is it possible to remove the storage for this ESR bit, and fix it > to one in ESR as well? > > I think it makes most sense that FO would be stuck to 1 in ESR as well. > It seems like only the relevant bits in SR should be storable in ESR, and > any bits that are ignored or are fixed should be able to be ignored. > Similarly, can the least significant 2 bits of the EPCR register be fixed > to zero? > > And I agree here, I think it should be possible to do what you propose here. > Why is the PPC register writable according to table 4-2? What happens > when it's written to? > > I can't come up with an use case where it would be of use to be able to write it and mor1kx doesn't support writing to it. > What happens when a misaligned address is written to the NPC register? > Does this trigger an alignment exception? > > Interesting question, and again I don't have a good answer, but in mor1kx the only case where it would trigger an alignment exception would be if you stall the processor, write NPC over debug if and unstall the processor. Because that's the only case where NPC is fed back to the fetch unit. I think you can disregard the case where actual software would write NPC, because even though it's possible to write it via the mtspr instruction, it's not "allowed" by the spec (i.e. behavior is undefined if you do so). Stefan
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