>On Mon, May 12, 2014 at 4:07 PM, Jonas Bonn <[email protected]> wrote: >> i) scratch space really just comes down to one or two per-cpu >> variables; we don't really need SPR's for this at all, but having some >> freely usable SPR's allows us to stash some per-cpu variables there >> instead of in memory
>JFYI (but probably you know), MIPS has 2 of them (k0 and k1). These are part >of the GPRs, though, which has the >disadvantage that you loose >2 (out of 32) GPRs, but the advantage that you can use them in most >instructions. Hi, isn't it, that those are shadowed? They are only visible during exceptions and the original registers are only accessible with special instructions, I think. For OpenRISC that would mean something like having R1 and R2 that are different during exceptions. Original R1 and R2 can then only accessed like: l.mfspr r1, r0, SPR_GPR1 The advantage of having R1 would be, that we already have the exception stack at hand, which would be neat. Bye, Stefan _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
