On Wed, Jul 23, 2014 at 10:28 AM, karthik gunda <[email protected]> wrote: > Hi Julius, > > I am karthik, We as a team have taken OR1200 processor from Opencores > and have modified the processors direct mapped cache with 4-way set > associative cache and LRU policy. We have also modified the Bus > Interface Units of the OR1200 Processor from Wishbone protocol to AXI > Protocol. All the work done by our team is also configured > successfully on FPGA. We would like to contribute back our work to > Opencores. Please guide me how our work can be contributed to > Opencores
Hi Karthik, That's some great sounding work. Have you developed any new testbenches and validation infrastructure around the modified core? That would also be extremely handy to have. Any documentation (perhaps an update to the existing OR1200 technical spec) would also be very welcome. Is it possible you could submit your work as a set of patches against a known version of the OR1200? Or is it available in a github or similar repository somewhere online? I'm CC'ing the OpenRISC mailing lists for further comment on this really cool work. Cheers Julius _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
