Template Version: @(#)sac_nextcase 1.64 07/13/07 SMI
This information is Copyright 2007 Sun Microsystems
1. Introduction
1.1. Project/Component Working Name:
Intel CPU and 5000/7300 Series Chipset FMA
1.2. Name of Document Author/Supplier:
Author: Gavin Maltby
1.3 Date of This Document:
13 October, 2007
4. Technical Description
This information is Copyright 2007 Sun Microsystems
1. Introduction
1.1. Project/Component Working Name:
Intel CPU and 5000/7300 Series Chipset FMA
1.2. Name of Document Author/Supplier:
Author: Adrian Frost
1.3 Date of This Document:
11 October, 2007
4. Technical Description
4.1. Project Summary
4.1.1 Project Description:
This case introduces FMA events for Intel x86 CPUs (i.e.,
Intel IA-32 and Intel 64 architectures) that implement the
Intel machine check architecture. This includes, but is not
limited to, the cpu models that are used in the upcoming
Sun Intel x64 systems.
This case also introduces FMA events for the Intel 5000 and
7300 series chipset memory-controller hubs (MCH), as also
used in the upcoming Sun Intel x64 systems (with the
exception of the Ultra 24 "Ursa" workstation which uses a
different chipset).
The associated FMA portfolio referenced below has already been
approved at FMA Portfolio Review.
4.1.2 Details:
CPU error handling and collection of telemetry for diagnosis
is performed by the generic MCA cpu module cpu.generic
(see PSARC/2007/591). The Intel model-specific support
layers on top of cpu.generic as module cpu_ms.GenuineIntel,
and provides a new ereport.cpu.intel.* subclass to ereports
which are otherwise unchanged from what cpu.generic has
provided. This new subclass allows a distinct set of
eversholt diagnosis rules to be applied instead of the
generic MCA rules, and a corresponding set of
fault.cpu.intel.* diagnoses may be produced.
A new driver 'intel_nb5000' provides support for the 5000 and
7300 series memory-controller hubs. This driver handles MCH
errors associated with the fully-buffered DIMMs that these
chipsets control, and raise telemetry in the ereport class
ereport.cpu.intel.nb.*. A set of eversholt rules consumes
this telemetry and may produce fault.memory.intel.* diagnoses.
The accompanying ercheck.html details all changes to the SMI
Events Registry. The approved FMA portfoliois here:
http://wikihome.sfbay.sun.com/fma-portfolio/Wiki.jsp?page=2007.022.Intel
4.9 I18N/L10N Impact:
A new FMA dictionary and .po/.mo "INTEL" is delivered.
5. Reference Documents:
PSARC/2007/591 Generic x86 Machine Check Architecture FMA
6. Resources and Schedule
6.4. Steering Committee requested information
6.4.1. Consolidation C-team Name:
ON
6.5. ARC review type: Automatic
6.6. ARC Exposure: open
