Template Version: @(#)sac_nextcase 1.68 02/23/09 SMI
This information is Copyright 2009 Sun Microsystems
1. Introduction
    1.1. Project/Component Working Name:
         Crossbow Import of Interrupt Affinity Interfaces
    1.2. Name of Document Author/Supplier:
         Author:  Rajagopal Kunhappan
    1.3  Date of This Document:
        07 July, 2009
4. Technical Description
This fasttrack covers the changes required for the Crossbow architecture
to import the DDI interfaces below, introduced by PSARC 2009/340. 
The interface taxonomy is Contracted Project Private. A copy of
the contract is placed in this case's directory.

Since the architectural impact of the interrupt affinity DDI interfaces and
its consumers has already been reviewed and approved with PSARC 2009/340,
I am marking this case as approved, pending the manager's emails
accepting the contracts terms. I'll be happy to set a timer if
needed.

typedef processorid_t ddi_intr_target_t;

int ddi_intr_get_affinity(ddi_intr_handle_t h, ddi_intr_target_t
    *tgt_p);
int ddi_intr_set_affinity(ddi_intr_handle_t h, ddi_intr_target_t tgt);

Crossbow framework will be a consumer of these interfaces.

More details on Crossbow requirements:
1) Crossbow provides a framework by which NIC resources such as Rx and
Tx rings are exposed to the MAC layer. The MAC layer doles out these
resources to VNICs when they get created while reserving a fixed amount
for the primary NIC. CPUs, on which the processing of packets take
place, can be specified at VNIC creation time or later.  If they are
specified, the interrupts associated with the Rx/Tx rings need to be
re-targeted to the specified CPUs. A mechanism by which a specific MSI-X
interrupt can be re-targeted to a different CPU is needed. This is for
the virtualization part of Crossbow.

2) For optimal performance of regular NICs (as well as VNICs), the poll
thread associated with an Rx ring should be bound to the same CPU as the
interrupt CPU. So given an interrupt handle and a CPU, a mechanism is
needed to re-target the interrupt to the specified CPU.

The above 2 requirements are addressed by the interfaces introduced in
PSARC 2009/340. 

6. Resources and Schedule
    6.4. Steering Committee requested information
        6.4.1. Consolidation C-team Name:
                ON
    6.5. ARC review type: Automatic
    6.6. ARC Exposure: open


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