Paul Durrant wrote: > > Hmm. That was integrated a long time after I did my implementations > (that's how long I've been waiting to integrate!). It looks like it has > the right semantics for x86 but the sparc implementation seems to be > n_writes; I'm not sure what that will do. > I'd be willing to drop this case and go with that interface though if > the sparc prefetch does what I need (i.e. pull data into cache for > multiple-read access). >
I found my sparcv9 manual! Prefetching for n_writes apparently implies exclusivity of the cache line in the CPU issuing the prefetch so would cause unnecessary cache line flushing in my use-case. How about I add prefetch_wrote_once() and prefetch_write_many() (the once and many mapping to nta amd t0 for x86, as with read) to the set and then change the consumers of prefetch64() (of which there only appears to be one) to use prefetch_write_many()? That way things continue to work as-is and we cover the full set of prefetched on the current set of supported CPUs. Paul -- ============================== Paul Durrant Senior Staff Engineer Solarflare Communications Inc. ==============================
