Is this on SPARC?
There is a branch delay on many RISC systems including SPARC, where the
instruction following the branch is also executed.
Usually the compiler can optimize away the nop, by putting some useful
work in the branch delay slot. But sometimes, it is not possible to
easily fill that. Also, if the compiler is not run with optimization
turned on, it might not bother to even *try* to fill those branch delay
slots.
Btw, many RISC systems also have other kinds of delays... such as load
delays (the value in the register might not be available in the next
instruction yet), etc. I don't remember which instructions in SPARC
have this kind of delay, as its been a while since I did much SPARC
assembler coding. I do know that branches do have that delay.
Of course, if you're seeing this behavior on x86 (a CISC architecture)
then I have no idea....
-- Garrett
On Tue, 2007-09-11 at 23:40 +0800, é¶æ· TaoJie wrote:
> Dear all:
>
> there's no sun studio mailling list in opensolaris.org, i raise my
> problem here :)
>
> a simple piece of code, 2 nested while loops, and some if statements
> inside each while loop.
>
> i compiled this program in Solaris with sun cc (sun studio 12) and
> gcc.
> and i compiled it in Debian with gcc as well.
>
> Then I dumped (disassembled) these 3 programs.
> I found that there were alway serveral nop instructions followed with
> the jmp instruction in the program generated by suncc.
> and this problem didn't exist in the other 2 program generated by gcc.
>
> err... Why does sun cc generate code using this pattern (a jmp
> followed by serveral nops)? For what?
>
> TIA
>
>
> Regards,
> TJ
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