Dear all: Suppose there's a 4-way Intel P4 or AMD Opteron SMP platform running Solaris 10. Or a Dual-Core/Quad-Core platform running Solaris 10.
There should be a global APIC on the mainboard, and each Processor/Core has its own local APIC. Is it right? When a external timer interrupt occurs, it is first sent to the global APIC, then the global APIC send out it to each Processor's local APIC. So, each processor will receive a timer interrupt, and handle it. Is it right? Since timer interrupt is a "global" interrupt (each online processor/core needs it), what about the other external interrupts? For example, interrupts from keyboard and from NIC? They are sent to global APIC first, then how does the global APIC decide which processor the interrupt should be sent to? TIA p.s. It's my first time touching SMP/CMT. Any useful & helpful articles? I've read Hennessy and Patterson's book, "Computer Architecture: A Quantitative Approach (4th Ed)". It just talks about the cache performance and cache coherance on SMP :-( I've read "Solaris Internals", chapter 16. It talks about memory-processor relationship as well. Kind Regards, TJ
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