Paul Jakma wrote:
> US IV+ and Opteron both have higher clock frequencies and larger L1
> caches per core and likely would be the better choice for compute
> intensive codes, including integer only.
> 
> Most definitely for FP codes. Plus both support SIMD instructions, VIS
> for former (for which Sun offer an SDK to make it easy to use without
> delving into asm), MMX/SSEn/3DNow for the latter - which iirc does have
> 128bit wide registers, though unfortunately for you does not have much
> in the way of 128bit arithmetical instructions.

Would it be possible that the next generation of SPARC CPUs will have
128bit integer registers ? Yes, I know - it will require another
revision of the ABI similar to SPARCv8 vs. SPARCv8a - but it would also
deliver some nice improvements for stuff like IPv6 processing, memory
copies, 3D applications (e.g. you could use 128bit integers instead of
(slower) floating-point for most 3D stuff) and many other
applications...

> > (outperforming the old E280R by more than factor three (E280R binary
> > was compiled with -xO4, T2000 binary was compiled with -xO2 so this is
> > no fair comparisation)), however the resolution isn't good enougth -
> > we would need something like 64.64bit fixed point math - or better:
> > Plain 128bit integers since it would help getting rid of the shifting
> > madness in the code (which makes it a nightmare to maintain).
> 
> There is a GNU Multi-Precision library (GMP - LGPL), which might save
> you some work.

Yes, I know... but last time I checked it didn't work with Sun Workshop
and using gcc for HPC stuff is useless.

> Though, it should be fairly easy to roll your own
> multi-word integer arithmetic functions if needs be.

Yes, but the code would become hard to maintain since this would be a
platform/CPU-specific optimisation...

----

Bye,
Roland

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