Hi,
On 05/01/07 11:52, Gavin Maltby wrote ...
... total nonsense!
For example, Studio 11 with -xarch=sparcv8plus can generate two
separate 32-bit ld instructions to load a single 64-bit value. An
atomic_load_64(3C) function would be useful to ensure that a single
ldx instruction is used.
You will always obtain the same result - the unit of cache coherency is
64 bytes (the size of a cacheline or cache sub-block in sparc systems).
The term "atomic" is sometimes used in this sense, but the more common
use is for exclusive atomic operations such as compare-and-swap.
Thanks to Greg for pointing out that I'm mistaken here. For instance
an interrupt could occur between the two 32-bit loads and in the
interim all sorts of things can happen that may affect the result
of the second load.
Apologies for the misleading info!
Gavin
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