As I alreday mentioned early this year, there is an ongoing work
on a free Sparc hardware implementation based on the T1 CPU design
data.
There is currently one person working on this project and he told me that
to the end of the year, there will be the first usable and sufficiently
complete verilog implementation.
The state to the end of this year will be the following:
- A complete description that may be loaded into a FPGA wil be ready.
- The features of this CPU will be:
- Sparc V8 (32 bit) IU
- FPU (later next year)
- one core with Chip multithreading
- if this works, 8 core versions running in bigger FPGAs
are possible.
At this time, first testa will be run on this real hardware using a development
board from the FPGA creator.
In spring, there is a plan to create ~ 10 self made boards (250 Euro each)
than may be distributed to several people.
The project needs help by people with the following interests:
- Porting OpenFirmware
- writing _small_ testprograms to verify correct behavior
- writing small performance analyse programs
- porting OpenSolaris or Netbsd
It seems that the main target at early times will be embedded boards.
The hardware designer has experiences with the desigh of low power hardware
as used in mobile phones and expects that a real silicon design will be cheap
and have a power consumption of 25-50% of a comparable ARM design.
Who is interested to help?
Who knows people or companies that are interested in cheaper and more power
effective embedded systems?
Jörg
--
EMail:[EMAIL PROTECTED] (home) Jörg Schilling D-13353 Berlin
[EMAIL PROTECTED] (uni)
[EMAIL PROTECTED] (work) Blog: http://schily.blogspot.com/
URL: http://cdrecord.berlios.de/old/private/ ftp://ftp.berlios.de/pub/schily
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