Gavin Maltby wrote: > Hi, > > Rocky wrote: >>> No. Bit 1 is not for C1E. C1E is a hardware feature >>> that you really don't want to disable. It should provide good power >>> management savings all on its own. >> >> OK, many thanks. Any other ideas on how to progress this? I'm >> getting the same syslog messages on a number of systems and SpeedStep >> is not available, different CPU's and Motherboards in each case. >> >> I really need as many power-saving things as possible for my always on >> servers. :) > > I'm no expert here, but I believe you can modify the dsl you dumped with > iasl > then recompile it and place it with appropriate filename in > /boot/acpi/tables which will then take precedence over the > BIOS-provided table. I did this for a Gigabyte AMD motherboard > that wasn't exporting a _PSS at all for the particular cpu > model I chose (home system). It sounds like something > similar should be possible here. Finding the correct > filename for the object was the hardest part.
I'm no ACPI expert either, but yes you can modify the dsl. Assuming fresh installs, you'd have to do this every time you installed your system(s). I contacted some folks at Intel about this problem and yes, this is a BIOS bug. It is one that they recognized from previous experience on Linux. Seems that on Linux (and presumably Windows) this bit is being enabled to work around the BIOS bug. I believe we will have to do the same thing for Solaris. There is currently work being done to add deep C-state support to Solaris. I believe that as part of that effort, the bit will be enabled. Sorry, I don't have the time frame. In the meantime, you might want to take Gavin's advice and modify the line in ssdt_1_CpuPm.dsl to be If (LEqual (And (PDC1, 0x09), 0x09)) recompile the file and place it under /boot/acpi/tables. Mark _______________________________________________ opensolaris-discuss mailing list [email protected]
