The branch master has been updated
       via  91cf7551a1dd4bc9a482c5577b5081adbae96ada (commit)
       via  b859d70d4a04db2e3b39b5c86cb6750d3c5b9593 (commit)
      from  cfe670732b63b875054aabd965a7bcecc6508657 (commit)


- Log -----------------------------------------------------------------
commit 91cf7551a1dd4bc9a482c5577b5081adbae96ada
Author: Andy Polyakov <[email protected]>
Date:   Mon Dec 21 14:29:02 2015 +0100

    Configure: refine 'reconf' logic.
    
    Reviewed-by: Rich Salz <[email protected]>

commit b859d70d4a04db2e3b39b5c86cb6750d3c5b9593
Author: Andy Polyakov <[email protected]>
Date:   Mon Dec 21 14:26:12 2015 +0100

    bn/asm/bn-c64xplus.asm: update commentary.
    
    Reviewed-by: Rich Salz <[email protected]>

-----------------------------------------------------------------------

Summary of changes:
 Configure                     | 2 +-
 crypto/bn/asm/bn-c64xplus.asm | 5 +++--
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/Configure b/Configure
index 84caaa3..ee8987e 100755
--- a/Configure
+++ b/Configure
@@ -1053,7 +1053,7 @@ PROCESS_ARGS:
                                                {
                                                $ENV{CROSS_COMPILE}=$1;
                                                }
-                                       elsif 
(/^CC=\s*(?:\$\(CROSS_COMPILE\))?(.*?)/)
+                                       elsif 
(/^CC=\s*(?:\$\(CROSS_COMPILE\))?(.*?)$/)
                                                {
                                                $ENV{CC}=$1;
                                                }
diff --git a/crypto/bn/asm/bn-c64xplus.asm b/crypto/bn/asm/bn-c64xplus.asm
index 7cd5881..7b72bff 100644
--- a/crypto/bn/asm/bn-c64xplus.asm
+++ b/crypto/bn/asm/bn-c64xplus.asm
@@ -284,8 +284,9 @@ _bn_mul_comba4:
        .if     0
        BNOP    sploopNxM?,3
        ;; Above mentioned m*2*(n+1)+10 does not apply in n=m=4 case,
-       ;; because of read-after-write penalties, it's rather
-       ;; n*2*(n+3)+10, or 66 cycles [plus various overheads]...
+       ;; because of low-counter effect, when prologue phase finishes
+       ;; before SPKERNEL instruction is reached. As result it's 25%
+       ;; slower than expected...
        MVK     4,B0            ; N, RILC
 ||     MVK     4,A0            ; M, outer loop counter
 ||     MV      ARG1,A5         ; copy ap
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