From: Andy Polyakov <[email protected]> Date: Sat, 01 Jun 2013 09:38:18 +0200
> I wonder about integer conditional move on integer condition. It > should be noted that sheer latency is of lesser concern, as long as > processor can efficiently handle several of them in > pipeline. Condition Codes Register would remain constant throughout > conditional move segment execution. "movcc" is fine, has a 1 cycle latency, and pipelines quite well. "movr" breaks the decode group, but still has a 1 cycle latency. ______________________________________________________________________ OpenSSL Project http://www.openssl.org Development Mailing List [email protected] Automated List Manager [email protected]
