1. RC4 implementation.
I wonder why key schedule prefetch is performed with 128 stride? As far as I understand 128 bytes is L2 line-size. But the loop is scheduled for L1D access, which [unilke L2] has 64 byte line-size. In other words it appears that prefetch fills only every second line in L1D. Is it intentional? I mean I realize that there is potential trade-off between amount of lfetch instructions vs. couple of stalls in the first loop spin... A.
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