As previously noted on this mailing list, the AES performance (without AES-NI) of v1.0.o on Intel Westmere chips seems a bit slow.
As also noted, this is price for side-channel countermeasures. Normally CBC performance is lower for small blocks sizes and "usual fast" for >=512B blocks. Intel has reintroduced Hyper-Threading, meaning that L1 cache is shared between two threads, which is why "usual fast" code is never engaged. cpuid.c output (thanks!) confirms that it's intentional.
In addition, RC4 seems a bit slow compared to previous Intel chips.
http://cvs.openssl.org/chngview?cn=19636. A. ______________________________________________________________________ OpenSSL Project http://www.openssl.org Development Mailing List [email protected] Automated List Manager [email protected]
