> Current mips systems have a variety of pipelines: > single-issue in-order, dual-issue in-order, and multi-issue with > dynamic scheduling. Code tuned this way for the R5000 is still > pretty good for all.
Well, dual-issue in-order is the one that can benefit. It's not unlike that it can sustain not more that one load in pair [at least that's what can be observed on other processors]. In this case it would pay off to spread and interleave computational and load instructions. > There are some new extract opcodes that could > maybe eliminate some masking steps. You must be referring to MIPS32 Release 2 specification. In context of aes-mips.pl 'extract' won't give any advantage, because 'shift right' and 'mask' would have to be replaced with 'extract' and 'shift left'. But it would be possible to use 'insert' in 1/4 of cases. Indeed, if we align tables at 1KB, 'insert' would allow to compose pointer to element in one step replacing 'shift left', 'mask' and 'addu'. New specification also adds 'rotate', which would make it possible to replace lwl/lwr pair with lw and 'rotate' (presumably better). Of course 'rotate' is totally usable in other cases, such as SHA. > There might be an opportunity > to replace most swl/swr pairs by aligned sw's. If you are referring to usw, unaligned store, my understanding is that it's pseudo-instructions, assembler generates swl/swr pair. If not, then elaborate. ______________________________________________________________________ OpenSSL Project http://www.openssl.org Development Mailing List [email protected] Automated List Manager [email protected]
