Hello all - This patch is a contribution to OpenSSL. It demonstrates an efficient implementation of AES-XTS, using Intel's AES-NI and AVX architecture. The performance improvement provided here is achieved via: a slightly improved reduction technique, encryption of several (here, 8) blocks in parallel, use of AVX, and unrolling. These ingredients can be used in different ways to improve the current OpenSSL performance of XTS. The performance: =============== AES-XTS performance: =================== The performance was measured by using openssl speed utility as follows: openssl speed -evp aes-128-xts Single thread performance in 1000s of B/S, for 8KB buffer: Core i7-2600K @3.4GHz *: OpenSSL Git[1]: 3448851.18 (0.99 Cycles/Byte) This patch: 4060259.32 (0.84 Cycles/Byte) Speedup: 1.18X Core i7-3770 @3.4GHz **: OpenSSL Git[1]: 3486178.83 (0.98 Cycles/Byte) This patch: 4072520.76 (0.83 Cycles/Byte) Speedup: 1.17X *Codename "Sandy Bridge" **Codename "Ivy Bridge"
[1] OpenSSL Gitweb: http://git.openssl.org/gitweb Note: This code will provide higher performance on the upcoming 3rd Generation Intel Core Processors (Codename Haswell) Developers and authors: *************************************************************************** Shay Gueron (1, 2), and Vlad Krasnov (1) (1) Intel Corporation, Israel Development Center, Haifa, Israel (2) University of Haifa, Israel *************************************************************************** Copyright(c) 2013, Intel Corp. --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies.
intel_aes_xts_v01.patch
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