Hello all, 

This patch is a contribution to OpenSSL.

It offers an efficient and constant-time implementation of 1024-bit and 
2048-bit Modular Exponentiation. When the patch is applied to the OpenSSL 
library, it accelerates RSA1024 (verify), RSA2048 (verify and sign), DSA1024 
(verify and sign), DSA2048 (verify and sign), DH1024 (GenKey, ComKey), DH2048 
(GenKey, ComKey), SRP (server and client side)

This extends the patch offered in [1]. 

The implementation is based on the "Redundant Representation" method (see [2]), 
that can accelerate modular exponentiation on sufficiently wide SIMD 
architecture. It uses the soon-to-come AVX2 instructions, and is intended to 
run on the coming Intel(R) architecture Codename "Haswell". 

The description of the AVX2 instructions can be found at: 
http://software.intel.com/en-us/blogs/2011/06/13/haswell-new-instruction-descriptions-now-available/
 

At the time this patch is published, "Haswell" processors are not yet 
commercially available. However, the correctness of the code can be checked 
using Intel's SDE tool: 
http://software.intel.com/en-us/articles/intel-software-development-emulator/ 

To compile the code, GCC version 4.7.0 or greater is required. 

The patch is enabled by running config with ./config -DRSAZ_AVX2

The performance benefits of this implementation could be measured when the 
Haswell processors become available. We predict a significant speedup, and the 
actual performance numbers will be published soon. 

References:
[1] S. Gueron, V. Krasnov: "[PATCH] Efficient and side channel analysis 
resistant 
512-bit and 1024-bit modular exponentiation for optimizing RSA1024 and RSA2048 
on x86_64 platforms", 
http://rt.openssl.org/Ticket/Display.html?id=2582&user=guest&pass=guest  

[2] Shay Gueron, Vlad Krasnov, "Software Implementation of Modular 
Exponentiation, 
Using Advanced Vector Instructions Architectures", Proceedings of The 
International 
Workshop on the Arithmetic of Finite Fields (WAIFI 2012), LNCS 7369: 119-135 
(2012).

Developers and authors:
***************************************************************************
Shay Gueron (1, 2), and Vlad Krasnov (1)
(1) Intel Corporation, Israel Development Center, Haifa, Israel
(2) University of Haifa, Israel
***************************************************************************
Copyright(c) 2013, Intel Corp.

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