Hello community, here is the log from the commit of package cpuid for openSUSE:Factory checked in at 2016-11-15 18:02:22 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/cpuid (Old) and /work/SRC/openSUSE:Factory/.cpuid.new (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "cpuid" Changes: -------- --- /work/SRC/openSUSE:Factory/cpuid/cpuid.changes 2016-09-07 11:48:24.000000000 +0200 +++ /work/SRC/openSUSE:Factory/.cpuid.new/cpuid.changes 2016-11-15 18:02:23.000000000 +0100 @@ -1,0 +2,30 @@ +Tue Nov 15 08:43:11 UTC 2016 - [email protected] + +- Update to new upstream release 20161114 +* cpuid.c: Added -l/--leaf and -s/--subleaf options to cause + cpuid to dump just the specified leaf and subleaf. If + -s/--subleaf is not specified, it is assumed to be 0. The + intended purpose for this is to display raw dumps of + not-yet-supported leaves. +* cpuid.c: Added AVX512DQ, AVX512IFMA, AVX512BW, AVX512VL, and + CLWB decoding to 7/ebx. +* cpuid.c: Added AVX512VBMI to 7/ecx. +* cpuid.c: Added print_f_0_edx to show L3 cache QoS monitoring + support. +* cpuid.c: Added total & local bandwidth monitoring to 0xf/1/edx. +* cpuid.c: Added 0x15/ecx nominal core crystal clock decoding. +* cpuid.c: In print_17_0_ebx, corrected reversed scheme + encodings. +* cpuid.c: Added synth decoding for Xeon D-1500 (Broadwell-DE) Y0 + stepping. +* cpuid.c: Added synth decoding comment about Braswell D1 + stepping, but its stepping number is not documented. +* cpuid.c: Added synth decoding for (0,6),(8,14) Kaby Lake + processors. +* cpuid.c: Added synth decoding for Apollo Lake processors. +* cpuid.c: Added vague synth decoding for (0,6),(9,14) Kaby Lake + processors. +* cpuid.c: Add AVX512_4VNNIW & AVX512_4FMAPS flags. +* cpuid.c: Add Knights Mill (KNM) CPUID. + +------------------------------------------------------------------- Old: ---- cpuid-20160814.src.tar.gz New: ---- cpuid-20161114.src.tar.gz ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ cpuid.spec ++++++ --- /var/tmp/diff_new_pack.kHaM7L/_old 2016-11-15 18:02:24.000000000 +0100 +++ /var/tmp/diff_new_pack.kHaM7L/_new 2016-11-15 18:02:24.000000000 +0100 @@ -18,7 +18,7 @@ Name: cpuid -Version: 20160814 +Version: 20161114 Release: 0 Summary: x86 CPU identification tool License: GPL-2.0+ ++++++ cpuid-20160814.src.tar.gz -> cpuid-20161114.src.tar.gz ++++++ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20160814/ChangeLog new/cpuid-20161114/ChangeLog --- old/cpuid-20160814/ChangeLog 2016-08-15 05:56:19.000000000 +0200 +++ new/cpuid-20161114/ChangeLog 2016-11-14 14:41:29.000000000 +0100 @@ -1,3 +1,48 @@ +Mon Nov 14 2016 Todd Allen <[email protected]> + * Made new release. + * cpuid.man: Added 334663 & 334820 spec updates. + +Sun Nov 13 2016 Todd Allen <[email protected]> + * cpuid.c: Fixed bug reported by Andrew Cooper where, in do_real, for + the 0xd leaf, the lower half of the valid bit set for XSS should've + used 0xd/1/ecx instead of 0xd/1/eax. Sadly, this bug affects raw + dumps too. + * cpuid.c: Added -l/--leaf and -s/--subleaf options to cause cpuid + to dump just the specified leaf and subleaf. If -s/--subleaf is not + specified, it is assumed to be 0. The intended purpose for this is + to display raw dumps of not-yet-supported leaves, or to workaround + bugs like the above. + +Sat Nov 12 2016 Todd Allen <[email protected]> + * cpuid.c: In bits_needed, add a further check for !defined(__ILP32__), + which should help with building a 32-bit version of cpuid on a 64-bit + system. + +Sat Nov 12 2016 Todd Allen <[email protected]> + * cpuid.c: Made editorial changes to Piotr Luc's patches (spelling, + capitalization, register order, comments, etc.). + * cpuid.c: Added AVX512DQ, AVX512IFMA, AVX512BW, AVX512VL, and CLWB + decoding to 7/ebx. + * cpuid.c: Added AVX512VBMI to 7/ecx. + * cpuid.c: Added print_f_0_edx to show L3 cache QoS monitoring support. + * cpuid.c: Added total & local bandwidth monitoring to 0xf/1/edx. + * cpuid.c: Added 0x15/ecx nominal core crystal clock decoding. + * cpuid.c: In print_17_0_ebx, corrected reversed scheme encodings. + * cpuid.c: Added synth decoding for Xeon D-1500 (Broadwell-DE) Y0 + stepping. + * cpuid.c: Added synth decoding comment about Braswell D1 stepping, but + its stepping number isn't documented. + * cpuid.c: Added synth decoding for (0,6),(8,14) Kaby Lake processors. + * cpuid.c: Added synth decoding for Apollo Lake processors. + * cpuid.c: Added vague synth decoding for (0,6),(9,14) Kaby Lake + processors. + * cpuid.c: Re-sorted (0,6),(5,7) Knights Landing to correct position. + * cpuid.c: Re-sorted (0,6),(5,15) Goldmont to correct position. + +Sat Oct 27 2016 Piotr Luc <[email protected]> + * cpuid.c: Add AVX512_4VNNIW & AVX512_4FMAPS flags. + * cpuid.c: Add Knights Mill (KNM) CPUID. + Sun Aug 14 2016 Todd Allen <[email protected]> * Made new release. * Makefile: Added clean rules to remove tarballs & rpm's with other diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20160814/FUTURE new/cpuid-20161114/FUTURE --- old/cpuid-20160814/FUTURE 2016-08-13 22:32:44.000000000 +0200 +++ new/cpuid-20161114/FUTURE 2016-11-14 14:36:02.000000000 +0100 @@ -3,7 +3,7 @@ Intel: Atom S12x9 (Briarwood) is based on Cedarview, but the Intel docs provide no CPUID identification values. And I can find no examples online. Does anyone know the CPUID family/model/steppings? -Intel: I can find no cpuid information on Atom C1000, Z2000, or E2000. +Intel: I can find no cpuid information on Atom C1000 or Z2000. (Possibly they are (0,6),(2,7) or (0,6),(3,5)?) AMD: Verify that (7,15, 0, 0, 1) really is steamroller. And are there more specific architecture names? diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20160814/Makefile new/cpuid-20161114/Makefile --- old/cpuid-20160814/Makefile 2016-08-14 19:46:59.000000000 +0200 +++ new/cpuid-20161114/Makefile 2016-11-14 14:36:59.000000000 +0100 @@ -7,7 +7,7 @@ CFL=$(CPPFLAGS) $(CFLAGS) $(CISA) -Wall -Wshadow -Wcast-align -Wredundant-decls -Wbad-function-cast -Wcast-qual -Wwrite-strings -Waggregate-return -Wstrict-prototypes -Wmissing-prototypes -D_FILE_OFFSET_BITS=64 -DVERSION=$(VERSION) PACKAGE=cpuid -VERSION=20160814 +VERSION=20161114 RELEASE=1 PROG=$(PACKAGE) diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20160814/cpuid.c new/cpuid-20161114/cpuid.c --- old/cpuid-20160814/cpuid.c 2016-08-15 05:54:53.000000000 +0200 +++ new/cpuid-20161114/cpuid.c 2016-11-14 02:57:53.000000000 +0100 @@ -2198,6 +2198,8 @@ FMQ ( 0, 6, 4, 7, sX, "Intel Xeon E3-1200 v4 (Broadwell), 14nm"); FM ( 0, 6, 4, 7, "Intel Core i7-5000 / Mobile Core i7-5000 / Xeon E3-1200 v4 (Broadwell), 14nm"); FM ( 0, 6, 4,10, "Intel Atom Z3400 (Merrifield), 22nm"); // no spec update; only 325462 Table 35-1 so far + // The (0,6),(4,12) processors also have a D1 stepping, but the + // Intel docs (332095) omit the stepping number. FMS ( 0, 6, 4,12, 0, "Intel Pentium N3000 / Celeron N3000 (Braswell C0), 14nm"); FM ( 0, 6, 4,12, "Intel Pentium N3000 / Celeron N3000 (Braswell), 14nm"); FMS ( 0, 6, 4,13, 0, "Intel Atom C2000 (Avoton A0/A1), 22nm"); @@ -2216,15 +2218,19 @@ FM ( 0, 6, 4,15, "Intel Core i7-6800K / i7-6900K / i7-6900X (Broadwell-E) / Xeon E5-1600 / E5-2500 / E5-4600 (Broadwell) / E7-4800 / E7-8800 v4 (Broadwell-EX), 14nm"); // So far, all these (0,6),(5,7) processors are stepping B0, but the // Intel docs (334646) omit the stepping number for B0. - FM ( 0, 6, 5, 7, "Intel Xeon Phi x200 (Knights Landing), 14nm"); FMS ( 0, 6, 5, 6, 1, "Intel Xeon D-1500 (Broadwell-DE U0), 14nm"); FMS ( 0, 6, 5, 6, 2, "Intel Xeon D-1500 (Broadwell-DE V1), 14nm"); FMS ( 0, 6, 5, 6, 3, "Intel Xeon D-1500 (Broadwell-DE V2), 14nm"); + FMS ( 0, 6, 5, 6, 4, "Intel Xeon D-1500 (Broadwell-DE Y0), 14nm"); FM ( 0, 6, 5, 6, "Intel Xeon D-1500 (Broadwell-DE), 14nm"); + FM ( 0, 6, 5, 7, "Intel Xeon Phi x200 (Knights Landing), 14nm"); FM ( 0, 6, 5,10, "Intel Atom Z3400 (Moorefield), 22nm"); // no spec update; only 325462 Table 35-1 so far - FM ( 0, 6, 5,12, "Intel Atom (Goldmont), 14nm"); // no spec update; only 325462 Table 35-1 so far + // Intel docs (334820) omit the stepping numbers for B0 & B1. + FMSQ( 0, 6, 5,12, 9, dP, "Intel Pentium N4000 / J4000 (Apollo Lake), 14nm"); + FMSQ( 0, 6, 5,12, 9, dC, "Intel Celeron N3000 / J3000 (Apollo Lake), 14nm"); + FMS ( 0, 6, 5,12, 9, "Intel Pentium N4000 / J4000 / Celeron N3000 / J3000 (Apollo Lake), 14nm"); + FM ( 0, 6, 5,12, "Intel Atom (Goldmont) / Pentium N4000 / J4000 / Celeron N3000 / J3000 (Apollo Lake), 14nm"); // no spec update for Goldmont; only 325462 Table 35-1 so far FM ( 0, 6, 5,13, "Intel Atom X3-C3000 (SoFIA), 22nm"); // no spec update; only 325462 Table 35-1 so far - FM ( 0, 6, 5,15, "Intel Atom (Goldmont), 14nm"); // no spec update; only 325462 Table 35-1 so far // Intel docs (332689,333133) omit the stepping numbers for (0,6),(5,14) // R0 & S0. FMQ ( 0, 6, 5,14, dc, "Intel Core i3-6000 / i5-6000 / i7-6000 (Skylake), 14nm"); @@ -2232,6 +2238,12 @@ FMQ ( 0, 6, 5,14, dC, "Intel Celeron G3900 (Skylake), 14nm"); FMQ ( 0, 6, 5,14, sX, "Intel Xeon E3-1200 v5 (Skylake), 14nm"); FM ( 0, 6, 5,14, "Intel Core i3-6000 / i5-6000 / i7-6000 / Pentium G4000 / Celeron G3900 / Xeon E3-1200 (Skylake), 14nm"); + FM ( 0, 6, 5,15, "Intel Atom (Goldmont), 14nm"); // no spec update; only 325462 Table 35-1 so far + FM ( 0, 6, 8, 5, "Intel Xeon Phi (Knights Mill), 14nm"); // no spec update; 325462 Table 35-1 is vague; Piotr Luc said it would be Knights Mill + // So far, all these (0,6),(8,14) processors are stepping H0, but the + // Intel docs (334663) omit the stepping number for H0. + FM ( 0, 6, 8,14, "Intel m3-7Y00 / i5-7Y00 / i7-7Y00 / i3-7000U / i5-7000U / i7-7000U (Kaby Lake), 14nm"); + FM ( 0, 6, 9,14, "Intel Core (Kaby Lake), 14nm"); // no spec update; only 325462 Table 35-1 so far FQ ( 0, 6, sX, "Intel Xeon (unknown model)"); FQ ( 0, 6, se, "Intel Xeon (unknown model)"); FQ ( 0, 6, MC, "Intel Mobile Celeron (unknown model)"); @@ -3421,7 +3433,7 @@ static int bits_needed(unsigned long v) { int result; -#ifdef __x86_64 +#if defined(__x86_64) && !defined(__ILP32__) asm("movq %[v],%%rax;" "movq $0,%%rcx;" "movl $0,%[result];" @@ -4069,7 +4081,6 @@ { "HWP energy performance preference" , 10, 10, bools }, { "HWP package level request" , 11, 11, bools }, { "HDC base registers" , 13, 13, bools }, - }; print_names(value, names, LENGTH(names, named_item), @@ -4121,15 +4132,20 @@ { "intel memory protection extensions" , 14, 14, bools }, { "PQE: platform quality of service enforce", 15, 15, bools }, { "AVX512F: AVX-512 foundation instructions", 16, 16, bools }, + { "AVX512DQ: double & quadword instructions", 17, 17, bools }, { "RDSEED instruction" , 18, 18, bools }, { "ADX instructions" , 19, 19, bools }, { "SMAP: supervisor mode access prevention" , 20, 20, bools }, + { "AVX512IFMA: fused multiply add" , 21, 21, bools }, { "CLFLUSHOPT instruction" , 23, 23, bools }, + { "CLWB instruction" , 24, 24, bools }, { "Intel processor trace" , 25, 25, bools }, { "AVX512PF: prefetch instructions" , 26, 26, bools }, { "AVX512ER: exponent & reciprocal instrs" , 27, 27, bools }, { "AVX512CD: conflict detection instrs" , 28, 28, bools }, { "SHA instructions" , 29, 29, bools }, + { "AVX512BW: byte & word instructions" , 30, 30, bools }, + { "AVX512VL: vector length" , 31, 31, bools }, }; print_names(value, names, LENGTH(names, named_item), @@ -4141,6 +4157,7 @@ { static named_item names[] = { { "PREFETCHWT1" , 0, 0, bools }, + { "AVX512VBMI: vector byte manipulation" , 1, 1, bools }, { "UMIP: user-mode instruction prevention" , 2, 2, bools }, { "PKU protection keys for user-mode" , 3, 3, bools }, { "OSPKE CR4.PKE and RDPKRU/WRPKRU" , 4, 4, bools }, @@ -4154,6 +4171,17 @@ } static void +print_7_edx(unsigned int value) +{ + static named_item names[] + = { { "AVX512_4VNNIW: neural network instrs" , 2, 2, bools }, + { "AVX512_4FMAPS: multiply acc single prec" , 3, 3, bools }, + }; + print_names(value, names, LENGTH(names, named_item), + /* max_len => */ 40); +} + +static void print_a_eax(unsigned int value) { static named_item names[] @@ -4388,10 +4416,23 @@ } static void +print_f_0_edx(unsigned int value) +{ + static named_item names[] + = { { "supports L3 cache QoS monitoring" , 0, 0, bools }, + }; + + print_names(value, names, LENGTH(names, named_item), + /* max_len => */ 0); +} + +static void print_f_1_edx(unsigned int value) { static named_item names[] = { { "supports L3 occupancy monitoring" , 0, 0, bools }, + { "supports L3 total bandwidth monitoring" , 1, 1, bools }, + { "supports L3 local bandwidth monitoring" , 2, 2, bools }, }; print_names(value, names, LENGTH(names, named_item), @@ -4414,7 +4455,7 @@ print_10_n_eax(unsigned int value) { static named_item names[] - = { { "length of capacity bit mask" , 0, 4, NIL_IMAGES }, + = { { "length of capacity bit mask - 1" , 0, 4, NIL_IMAGES }, }; print_names(value, names, LENGTH(names, named_item), @@ -4589,8 +4630,8 @@ static void print_17_0_ebx(unsigned int value) { - static ccstring schemes[] = { /* 0 => */ "industry standard", - /* 1 => */ "assigned by intel" }; + static ccstring schemes[] = { /* 0 => */ "assigned by intel", + /* 1 => */ "industry standard" }; static named_item names[] = { { "vendor id" , 0, 15, NIL_IMAGES }, @@ -5813,6 +5854,13 @@ printf(" of from executions of the cpuid" " instruction.\n"); printf(" If FILE is '-', read from stdin.\n"); + printf(" -l V, --leaf=V display information for the single specified" + " leaf.\n"); + printf(" If -s/--subleaf is not specified, 0 is" + " assumed.\n"); + printf(" -s V, --subleaf=V display information for the single specified" + " subleaf.\n"); + printf(" It requires -l/--leaf.\n"); printf(" -h, -H, --help display this help information\n"); printf(" -i, --inst use the CPUID instruction: The information" " it provides\n"); @@ -6038,6 +6086,7 @@ if (try == 0) { print_7_ebx(words[WORD_EBX]); print_7_ecx(words[WORD_ECX]); + print_7_edx(words[WORD_EDX]); } else { /* Reserved: DO NOTHING */ } @@ -6096,6 +6145,7 @@ if (try == 0) { printf(" Quality of Service Monitoring Resource Type (0xf/0):\n"); printf(" Maximum range of RMID = %u\n", words[WORD_EBX]); + print_f_0_edx(words[WORD_EDX]); } else if (try == 1) { printf(" L3 Cache Quality of Service Monitoring (0xf/1):\n"); printf(" Conversion factor from IA32_QM_CTR to bytes = %u\n", @@ -6165,6 +6215,7 @@ printf(" Time Stamp Counter/Core Crystal Clock Information (0x15):\n"); printf(" TSC/clock ratio = %u/%u\n", words[WORD_EBX], words[WORD_EAX]); + printf(" nominal core crystal clock = %u Hz\n", words[WORD_ECX]); } else if (reg == 0x16) { printf(" Processor Frequency Information (0x16):\n"); print_16_eax(words[WORD_EAX]); @@ -6628,6 +6679,37 @@ } static void +do_real_one(unsigned int reg, + unsigned int try, + boolean one_cpu, + boolean inst, + boolean raw, + boolean debug) +{ + unsigned int cpu; + + for (cpu = 0;; cpu++) { + int cpuid_fd = -1; + code_stash_t stash = NIL_STASH; + + if (one_cpu && cpu > 0) break; + + cpuid_fd = real_setup(cpu, one_cpu, inst); + if (cpuid_fd == -1) break; + + if (inst && one_cpu) { + printf("CPU:\n"); + } else { + printf("CPU %u:\n", cpu); + } + + unsigned int words[WORD_NUM]; + real_get(cpuid_fd, reg, words, try, FALSE); + print_reg(reg, words, raw, try, &stash); + } +} + +static void do_real(boolean one_cpu, boolean inst, boolean raw, @@ -6712,7 +6794,7 @@ ** Intel: ** For ecx values 2..63, the leaf is present if the corresponding ** bit is present in the bit catenation of 0xd/0/edx + 0xd/0/eax, - ** or the bit catenation of 0xd/1/edx + 0xd/1/eax. + ** or the bit catenation of 0xd/1/edx + 0xd/1/ecx. ** AMD: ** Only 4 ecx values are defined and it's gappy. It's unclear ** what the upper bound of any loop would be, so it seems @@ -6725,7 +6807,7 @@ real_get(cpuid_fd, reg, words, 1, FALSE); print_reg(reg, words, raw, 1, &stash); unsigned long long valid_xss - = ((unsigned long long)words[WORD_EDX] << 32) | words[WORD_EAX]; + = ((unsigned long long)words[WORD_EDX] << 32) | words[WORD_ECX]; unsigned long long valid_tries = valid_xcr0 | valid_xss; unsigned int try; for (try = 2; try < 63; try++) { @@ -7036,7 +7118,7 @@ main(int argc, string argv[]) { - static ccstring shortopts = "+hH1ikrdf:v"; + static ccstring shortopts = "+hH1ikrdf:vl:s:"; static const struct option longopts[] = { { "help", no_argument, NULL, 'h' }, { "one-cpu", no_argument, NULL, '1' }, @@ -7046,16 +7128,22 @@ { "debug", no_argument, NULL, 'd' }, { "file", required_argument, NULL, 'f' }, { "version", no_argument, NULL, 'v' }, + { "leaf", required_argument, NULL, 'l' }, + { "subleaf", required_argument, NULL, 's' }, { NULL, no_argument, NULL, '\0' } }; - boolean opt_one_cpu = FALSE; - boolean opt_inst = FALSE; - boolean opt_kernel = FALSE; - boolean opt_raw = FALSE; - boolean opt_debug = FALSE; - cstring opt_filename = NULL; - boolean opt_version = FALSE; + boolean opt_one_cpu = FALSE; + boolean opt_inst = FALSE; + boolean opt_kernel = FALSE; + boolean opt_raw = FALSE; + boolean opt_debug = FALSE; + cstring opt_filename = NULL; + boolean opt_version = FALSE; + boolean opt_leaf = FALSE; + unsigned long opt_leaf_val = 0; + boolean opt_subleaf = FALSE; + unsigned long opt_subleaf_val = 0; program = strrchr(argv[0], '/'); if (program == NULL) { @@ -7098,6 +7186,34 @@ case 'v': opt_version = TRUE; break; + case 'l': + opt_leaf = TRUE; + { + errno = 0; + char* endptr = NULL; + opt_leaf_val = strtoul(optarg, &endptr, 0); + if (errno != 0) { + fprintf(stderr, + "%s: argument to -l/--leaf not understood: %s\n", + program, argv[optind-1]); + exit(1); + } + } + break; + case 's': + opt_subleaf = TRUE; + { + errno = 0; + char* endptr = NULL; + opt_subleaf_val = strtoul(optarg, &endptr, 0); + if (errno != 0) { + fprintf(stderr, + "%s: argument to -s/--subleaf not understood: %s\n", + program, argv[optind-1]); + exit(1); + } + } + break; case '?': default: if (optopt == '\0') { @@ -7133,6 +7249,20 @@ exit(1); } + if (opt_filename != NULL && opt_leaf) { + fprintf(stderr, + "%s: -f/--file and -l/--leaf are incompatible options\n", + program); + exit(1); + } + + if (opt_subleaf && !opt_leaf) { + fprintf(stderr, + "%s: -s/--subleaf requires that -l/--leaf also be specified\n", + program); + exit(1); + } + // Default to -i. So use inst unless -k is specified. boolean inst = !opt_kernel; @@ -7141,6 +7271,9 @@ } else { if (opt_filename != NULL) { do_file(opt_filename, opt_raw, opt_debug); + } else if (opt_leaf) { + do_real_one(opt_leaf_val, opt_subleaf_val, + opt_one_cpu, inst, opt_raw, opt_debug); } else { do_real(opt_one_cpu, inst, opt_raw, opt_debug); } diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20160814/cpuid.man new/cpuid-20161114/cpuid.man --- old/cpuid-20160814/cpuid.man 2016-08-15 05:56:06.000000000 +0200 +++ new/cpuid-20161114/cpuid.man 2016-11-14 14:40:35.000000000 +0100 @@ -1,7 +1,7 @@ .\" -.\" $Id: cpuid.man,v 20151017 2016/08/14 21:55:40 todd $ +.\" $Id: cpuid.man,v 20161114 2016/08/14 06:34:48 todd $ .\" -.TH CPUID 1 "14 Aug 2016" "20160814" +.TH CPUID 1 "14 Nov 2016" "201601114" .SH NAME cpuid \- Dump CPUID information for each CPU .SH SYNOPSIS @@ -414,6 +414,11 @@ .br 334646: Intel Xeon Phi Processor x200 Product Family Preliminary Specification Update +.br +334663: 7th Generation Intel Processor Family Specification Update Supporting +7th Generation Intel Core Processor Families based on U/Y-Processor Line +.br +334820: Intel Pentium and Celeron Processor N- and J- Series Specification Update .RE Information on the CPUID instruction and on specific CPUs is available from diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20160814/cpuid.spec new/cpuid-20161114/cpuid.spec --- old/cpuid-20160814/cpuid.spec 2016-08-15 05:58:13.000000000 +0200 +++ new/cpuid-20161114/cpuid.spec 2016-11-14 14:42:20.000000000 +0100 @@ -1,4 +1,4 @@ -%define version 20160814 +%define version 20161114 %define release 1 Summary: dumps CPUID information about the CPU(s) Name: cpuid
