Hello community,

here is the log from the commit of package kernel-source for openSUSE:Factory 
checked in at 2017-03-16 09:33:02
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Comparing /work/SRC/openSUSE:Factory/kernel-source (Old)
 and      /work/SRC/openSUSE:Factory/.kernel-source.new (New)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

Package is "kernel-source"

Thu Mar 16 09:33:02 2017 rev:355 rq:479438 version:4.10.3

Changes:
--------
--- /work/SRC/openSUSE:Factory/kernel-source/dtb-aarch64.changes        
2017-03-15 01:59:50.736145332 +0100
+++ /work/SRC/openSUSE:Factory/.kernel-source.new/dtb-aarch64.changes   
2017-03-16 09:33:04.618611051 +0100
@@ -1,0 +2,11 @@
+Wed Mar 15 08:47:00 CET 2017 - [email protected]
+
+- Linux 4.10.3 (CVE-2017-2636 bnc#1012628 bnc#1027565
+  boo#1027378).
+- Delete
+  patches.fixes/drm-amdgpu-revert-update-tile-table-for-oland-hainan.patch.
+- Delete
+  patches.fixes/tty-n_hdlc-get-rid-of-racy-n_hdlc.tbuf.patch.
+- commit 0c9f8e4
+
+-------------------------------------------------------------------
dtb-armv6l.changes: same change
dtb-armv7l.changes: same change
kernel-64kb.changes: same change
kernel-debug.changes: same change
kernel-default.changes: same change
kernel-docs.changes: same change
kernel-lpae.changes: same change
kernel-obs-build.changes: same change
kernel-obs-qa.changes: same change
kernel-pae.changes: same change
kernel-source.changes: same change
kernel-syms.changes: same change
kernel-syzkaller.changes: same change
kernel-vanilla.changes: same change

++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

Other differences:
------------------
++++++ dtb-aarch64.spec ++++++
--- /var/tmp/diff_new_pack.DznNGi/_old  2017-03-16 09:33:10.665754813 +0100
+++ /var/tmp/diff_new_pack.DznNGi/_new  2017-03-16 09:33:10.669754246 +0100
@@ -16,15 +16,15 @@
 #
 
 
-%define patchversion 4.10.2
+%define patchversion 4.10.3
 %define vanilla_only 0
 
 %include %_sourcedir/kernel-spec-macros
 
 Name:           dtb-aarch64
-Version:        4.10.2
+Version:        4.10.3
 %if 0%{?is_kotd}
-Release:        <RELEASE>.gbfb2d22
+Release:        <RELEASE>.g0c9f8e4
 %else
 Release:        0
 %endif

dtb-armv6l.spec: same change
dtb-armv7l.spec: same change
++++++ kernel-64kb.spec ++++++
--- /var/tmp/diff_new_pack.DznNGi/_old  2017-03-16 09:33:10.761741222 +0100
+++ /var/tmp/diff_new_pack.DznNGi/_new  2017-03-16 09:33:10.761741222 +0100
@@ -18,7 +18,7 @@
 
 
 %define srcversion 4.10
-%define patchversion 4.10.2
+%define patchversion 4.10.3
 %define variant %{nil}
 %define vanilla_only 0
 
@@ -58,9 +58,9 @@
 Summary:        Kernel with 64kb PAGE_SIZE
 License:        GPL-2.0
 Group:          System/Kernel
-Version:        4.10.2
+Version:        4.10.3
 %if 0%{?is_kotd}
-Release:        <RELEASE>.gbfb2d22
+Release:        <RELEASE>.g0c9f8e4
 %else
 Release:        0
 %endif

kernel-debug.spec: same change
kernel-default.spec: same change
++++++ kernel-docs.spec ++++++
--- /var/tmp/diff_new_pack.DznNGi/_old  2017-03-16 09:33:10.841729896 +0100
+++ /var/tmp/diff_new_pack.DznNGi/_new  2017-03-16 09:33:10.845729330 +0100
@@ -16,7 +16,7 @@
 #
 
 
-%define patchversion 4.10.2
+%define patchversion 4.10.3
 %define variant %{nil}
 
 %include %_sourcedir/kernel-spec-macros
@@ -42,9 +42,9 @@
 Summary:        Kernel Documentation (man pages)
 License:        GPL-2.0
 Group:          Documentation/Man
-Version:        4.10.2
+Version:        4.10.3
 %if 0%{?is_kotd}
-Release:        <RELEASE>.gbfb2d22
+Release:        <RELEASE>.g0c9f8e4
 %else
 Release:        0
 %endif

++++++ kernel-lpae.spec ++++++
--- /var/tmp/diff_new_pack.DznNGi/_old  2017-03-16 09:33:10.869725932 +0100
+++ /var/tmp/diff_new_pack.DznNGi/_new  2017-03-16 09:33:10.873725366 +0100
@@ -18,7 +18,7 @@
 
 
 %define srcversion 4.10
-%define patchversion 4.10.2
+%define patchversion 4.10.3
 %define variant %{nil}
 %define vanilla_only 0
 
@@ -58,9 +58,9 @@
 Summary:        Kernel for LPAE enabled systems
 License:        GPL-2.0
 Group:          System/Kernel
-Version:        4.10.2
+Version:        4.10.3
 %if 0%{?is_kotd}
-Release:        <RELEASE>.gbfb2d22
+Release:        <RELEASE>.g0c9f8e4
 %else
 Release:        0
 %endif

++++++ kernel-obs-build.spec ++++++
--- /var/tmp/diff_new_pack.DznNGi/_old  2017-03-16 09:33:10.897721968 +0100
+++ /var/tmp/diff_new_pack.DznNGi/_new  2017-03-16 09:33:10.897721968 +0100
@@ -19,7 +19,7 @@
 
 #!BuildIgnore: post-build-checks
 
-%define patchversion 4.10.2
+%define patchversion 4.10.3
 %define variant %{nil}
 %define vanilla_only 0
 
@@ -57,9 +57,9 @@
 Summary:        package kernel and initrd for OBS VM builds
 License:        GPL-2.0
 Group:          SLES
-Version:        4.10.2
+Version:        4.10.3
 %if 0%{?is_kotd}
-Release:        <RELEASE>.gbfb2d22
+Release:        <RELEASE>.g0c9f8e4
 %else
 Release:        0
 %endif

++++++ kernel-obs-qa.spec ++++++
--- /var/tmp/diff_new_pack.DznNGi/_old  2017-03-16 09:33:10.921718570 +0100
+++ /var/tmp/diff_new_pack.DznNGi/_new  2017-03-16 09:33:10.921718570 +0100
@@ -17,7 +17,7 @@
 # needsrootforbuild
 
 
-%define patchversion 4.10.2
+%define patchversion 4.10.3
 %define variant %{nil}
 
 %include %_sourcedir/kernel-spec-macros
@@ -36,9 +36,9 @@
 Summary:        Basic QA tests for the kernel
 License:        GPL-2.0
 Group:          SLES
-Version:        4.10.2
+Version:        4.10.3
 %if 0%{?is_kotd}
-Release:        <RELEASE>.gbfb2d22
+Release:        <RELEASE>.g0c9f8e4
 %else
 Release:        0
 %endif

++++++ kernel-pae.spec ++++++
--- /var/tmp/diff_new_pack.DznNGi/_old  2017-03-16 09:33:10.945715173 +0100
+++ /var/tmp/diff_new_pack.DznNGi/_new  2017-03-16 09:33:10.945715173 +0100
@@ -18,7 +18,7 @@
 
 
 %define srcversion 4.10
-%define patchversion 4.10.2
+%define patchversion 4.10.3
 %define variant %{nil}
 %define vanilla_only 0
 
@@ -58,9 +58,9 @@
 Summary:        Kernel with PAE Support
 License:        GPL-2.0
 Group:          System/Kernel
-Version:        4.10.2
+Version:        4.10.3
 %if 0%{?is_kotd}
-Release:        <RELEASE>.gbfb2d22
+Release:        <RELEASE>.g0c9f8e4
 %else
 Release:        0
 %endif

++++++ kernel-source.spec ++++++
--- /var/tmp/diff_new_pack.DznNGi/_old  2017-03-16 09:33:10.965712341 +0100
+++ /var/tmp/diff_new_pack.DznNGi/_new  2017-03-16 09:33:10.969711775 +0100
@@ -18,7 +18,7 @@
 
 
 %define srcversion 4.10
-%define patchversion 4.10.2
+%define patchversion 4.10.3
 %define variant %{nil}
 %define vanilla_only 0
 
@@ -30,9 +30,9 @@
 Summary:        The Linux Kernel Sources
 License:        GPL-2.0
 Group:          Development/Sources
-Version:        4.10.2
+Version:        4.10.3
 %if 0%{?is_kotd}
-Release:        <RELEASE>.gbfb2d22
+Release:        <RELEASE>.g0c9f8e4
 %else
 Release:        0
 %endif

++++++ kernel-syms.spec ++++++
--- /var/tmp/diff_new_pack.DznNGi/_old  2017-03-16 09:33:10.997707811 +0100
+++ /var/tmp/diff_new_pack.DznNGi/_new  2017-03-16 09:33:11.001707244 +0100
@@ -24,10 +24,10 @@
 Summary:        Kernel Symbol Versions (modversions)
 License:        GPL-2.0
 Group:          Development/Sources
-Version:        4.10.2
+Version:        4.10.3
 %if %using_buildservice
 %if 0%{?is_kotd}
-Release:        <RELEASE>.gbfb2d22
+Release:        <RELEASE>.g0c9f8e4
 %else
 Release:        0
 %endif

++++++ kernel-syzkaller.spec ++++++
--- /var/tmp/diff_new_pack.DznNGi/_old  2017-03-16 09:33:11.021704412 +0100
+++ /var/tmp/diff_new_pack.DznNGi/_new  2017-03-16 09:33:11.025703847 +0100
@@ -18,7 +18,7 @@
 
 
 %define srcversion 4.10
-%define patchversion 4.10.2
+%define patchversion 4.10.3
 %define variant %{nil}
 %define vanilla_only 0
 
@@ -58,9 +58,9 @@
 Summary:        Kernel used for fuzzing by syzkaller
 License:        GPL-2.0
 Group:          System/Kernel
-Version:        4.10.2
+Version:        4.10.3
 %if 0%{?is_kotd}
-Release:        <RELEASE>.gbfb2d22
+Release:        <RELEASE>.g0c9f8e4
 %else
 Release:        0
 %endif

kernel-vanilla.spec: same change
++++++ patches.fixes.tar.bz2 ++++++
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' 
'--exclude=.svnignore' 
old/patches.fixes/drm-amdgpu-revert-update-tile-table-for-oland-hainan.patch 
new/patches.fixes/drm-amdgpu-revert-update-tile-table-for-oland-hainan.patch
--- 
old/patches.fixes/drm-amdgpu-revert-update-tile-table-for-oland-hainan.patch    
    2017-03-09 17:48:39.000000000 +0100
+++ 
new/patches.fixes/drm-amdgpu-revert-update-tile-table-for-oland-hainan.patch    
    1970-01-01 01:00:00.000000000 +0100
@@ -1,458 +0,0 @@
-From: Jean Delvare <[email protected]>
-Subject: Revert "drm/amdgpu: update tile table for oland/hainan"
-References: boo#1027378
-Patch-mainline: No, will be fixed differently in v4.11
-
-Revert commit f8d9422ef80c ("drm/amdgpu: update tile table for
-oland/hainan") as it is causing ugly visual artefacts on at least
-Oland. This is only an optimization so we can live without it.
-
-This fixes kernel bug #194761:
-amdgpu driver breaks on Oland (SI)
-https://bugzilla.kernel.org/show_bug.cgi?id=194761
-
-Signed-off-by: Jean Delvare <[email protected]>
-Fixes: f8d9422ef80c ("drm/amdgpu: update tile table for oland/hainan")
-Acked-by: Alex Deucher <[email protected]>
-Cc: Flora Cui <[email protected]>
-Cc: Junwei Zhang <[email protected]>
----
-Note: This is for stable v4.10 branch only. v4.11 and later have a
-different fix, but it's much larger and more intrusive so not suitable
-for a stable branch.
-
- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c |  330 
++++++++++++++--------------------
- 1 file changed, 139 insertions(+), 191 deletions(-)
-
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
-@@ -708,290 +708,238 @@ static void gfx_v6_0_tiling_mode_table_i
-               for (reg_offset = 0; reg_offset < num_tile_mode_states; 
reg_offset++) {
-                       switch (reg_offset) {
-                       case 0:
--                              gb_tile_moden = 
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
--                                               
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--                                               PIPE_CONFIG(ADDR_SURF_P2) |
-+                              gb_tile_moden = 
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+                                               
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-+                                               PIPE_CONFIG(ADDR_SURF_P4_8x16) 
|
-                                                
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-+                                               NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--                                               NUM_BANKS(ADDR_SURF_16_BANK));
-+                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
-                               break;
-                       case 1:
--                              gb_tile_moden = 
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
--                                               
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--                                               PIPE_CONFIG(ADDR_SURF_P2) |
-+                              gb_tile_moden = 
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+                                               
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-+                                               PIPE_CONFIG(ADDR_SURF_P4_8x16) 
|
-                                                
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
-+                                               NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--                                               NUM_BANKS(ADDR_SURF_16_BANK));
-+                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
-                               break;
-                       case 2:
--                              gb_tile_moden = 
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
--                                               
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--                                               PIPE_CONFIG(ADDR_SURF_P2) |
-+                              gb_tile_moden = 
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+                                               
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-+                                               PIPE_CONFIG(ADDR_SURF_P4_8x16) 
|
-                                                
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-+                                               NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--                                               NUM_BANKS(ADDR_SURF_16_BANK));
-+                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
-                               break;
-                       case 3:
--                              gb_tile_moden = 
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
--                                               
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--                                               PIPE_CONFIG(ADDR_SURF_P2) |
-+                              gb_tile_moden = 
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+                                               
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-+                                               PIPE_CONFIG(ADDR_SURF_P4_8x16) 
|
-+                                               
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
-+                                               NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--                                               
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--                                               NUM_BANKS(ADDR_SURF_8_BANK) |
--                                               
TILE_SPLIT(split_equal_to_row_size));
-+                                               
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
-                               break;
-                       case 4:
--                              gb_tile_moden = 
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
--                                               
ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--                                               PIPE_CONFIG(ADDR_SURF_P2));
-+                              gb_tile_moden = 
(ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+                                               
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-+                                               PIPE_CONFIG(ADDR_SURF_P4_8x16) 
|
-+                                               
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-+                                               NUM_BANKS(ADDR_SURF_16_BANK) |
-+                                               
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+                                               
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 5:
--                              gb_tile_moden = 
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
--                                               
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--                                               PIPE_CONFIG(ADDR_SURF_P2) |
--                                               
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-+                              gb_tile_moden = 
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+                                               
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-+                                               PIPE_CONFIG(ADDR_SURF_P4_8x16) 
|
-+                                               
TILE_SPLIT(split_equal_to_row_size) |
-+                                               NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--                                               
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--                                               NUM_BANKS(ADDR_SURF_8_BANK));
-+                                               
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 6:
--                              gb_tile_moden = 
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
--                                               
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--                                               PIPE_CONFIG(ADDR_SURF_P2) |
--                                               
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-+                              gb_tile_moden = 
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+                                               
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-+                                               PIPE_CONFIG(ADDR_SURF_P4_8x16) 
|
-+                                               
TILE_SPLIT(split_equal_to_row_size) |
-+                                               NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--                                               
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--                                               NUM_BANKS(ADDR_SURF_8_BANK));
-+                                               
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 7:
--                              gb_tile_moden = 
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
--                                               
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--                                               PIPE_CONFIG(ADDR_SURF_P2) |
--                                               
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
-+                              gb_tile_moden = 
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+                                               
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-+                                               PIPE_CONFIG(ADDR_SURF_P4_8x16) 
|
-+                                               
TILE_SPLIT(split_equal_to_row_size) |
-+                                               NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--                                               
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--                                               NUM_BANKS(ADDR_SURF_4_BANK));
-+                                               
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
-                               break;
-                       case 8:
--                              gb_tile_moden = 
(ARRAY_MODE(ARRAY_LINEAR_ALIGNED));
-+                              gb_tile_moden = 
(ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
-+                                               
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+                                               PIPE_CONFIG(ADDR_SURF_P4_8x16) 
|
-+                                               
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-+                                               NUM_BANKS(ADDR_SURF_16_BANK) |
-+                                               
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+                                               
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 9:
--                              gb_tile_moden = 
(MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
--                                               
ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--                                               PIPE_CONFIG(ADDR_SURF_P2));
-+                              gb_tile_moden = 
(ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+                                               
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+                                               PIPE_CONFIG(ADDR_SURF_P4_8x16) 
|
-+                                               
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-+                                               NUM_BANKS(ADDR_SURF_16_BANK) |
-+                                               
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+                                               
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 10:
--                              gb_tile_moden = 
(MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
--                                               
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--                                               PIPE_CONFIG(ADDR_SURF_P2) |
-+                              gb_tile_moden = 
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+                                               
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+                                               PIPE_CONFIG(ADDR_SURF_P4_8x16) 
|
-                                                
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-+                                               NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--                                               NUM_BANKS(ADDR_SURF_16_BANK));
-+                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
-                               break;
-                       case 11:
--                              gb_tile_moden = 
(MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
--                                               
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--                                               PIPE_CONFIG(ADDR_SURF_P2) |
-+                              gb_tile_moden = 
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+                                               
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+                                               PIPE_CONFIG(ADDR_SURF_P4_8x16) 
|
-                                                
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-+                                               NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--                                               NUM_BANKS(ADDR_SURF_16_BANK));
-+                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 12:
--                              gb_tile_moden = 
(MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
--                                               
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--                                               PIPE_CONFIG(ADDR_SURF_P2) |
-+                              gb_tile_moden = 
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+                                               
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+                                               PIPE_CONFIG(ADDR_SURF_P4_8x16) 
|
-                                                
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-+                                               NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--                                               NUM_BANKS(ADDR_SURF_16_BANK));
-+                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 13:
--                              gb_tile_moden = 
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--                                               
ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--                                               PIPE_CONFIG(ADDR_SURF_P2));
-+                              gb_tile_moden = 
(ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+                                               
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-+                                               PIPE_CONFIG(ADDR_SURF_P4_8x16) 
|
-+                                               
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-+                                               NUM_BANKS(ADDR_SURF_16_BANK) |
-+                                               
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+                                               
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 14:
--                              gb_tile_moden = 
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--                                               
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--                                               PIPE_CONFIG(ADDR_SURF_P2) |
-+                              gb_tile_moden = 
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+                                               
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-+                                               PIPE_CONFIG(ADDR_SURF_P4_8x16) 
|
-                                                
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-+                                               NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--                                               NUM_BANKS(ADDR_SURF_16_BANK));
-+                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 15:
--                              gb_tile_moden = 
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--                                               
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--                                               PIPE_CONFIG(ADDR_SURF_P2) |
-+                              gb_tile_moden = 
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+                                               
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-+                                               PIPE_CONFIG(ADDR_SURF_P4_8x16) 
|
-                                                
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-+                                               NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--                                               NUM_BANKS(ADDR_SURF_16_BANK));
-+                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 16:
--                              gb_tile_moden = 
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--                                               
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--                                               PIPE_CONFIG(ADDR_SURF_P2) |
-+                              gb_tile_moden = 
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+                                               
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-+                                               PIPE_CONFIG(ADDR_SURF_P4_8x16) 
|
-                                                
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-+                                               NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--                                               NUM_BANKS(ADDR_SURF_16_BANK));
-+                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 17:
--                              gb_tile_moden = 
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--                                               
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--                                               PIPE_CONFIG(ADDR_SURF_P2) |
--                                               
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--                                               
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--                                               NUM_BANKS(ADDR_SURF_16_BANK) |
--                                               
TILE_SPLIT(split_equal_to_row_size));
--                              break;
--                      case 18:
--                              gb_tile_moden = 
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--                                               
ARRAY_MODE(ARRAY_1D_TILED_THICK) |
--                                               PIPE_CONFIG(ADDR_SURF_P2));
--                              break;
--                      case 19:
--                              gb_tile_moden = 
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--                                               
ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
--                                               PIPE_CONFIG(ADDR_SURF_P2) |
--                                               
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--                                               
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+                              gb_tile_moden = 
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+                                               
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-+                                               PIPE_CONFIG(ADDR_SURF_P4_8x16) 
|
-+                                               
TILE_SPLIT(split_equal_to_row_size) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
--                                               
TILE_SPLIT(split_equal_to_row_size));
--                              break;
--                      case 20:
--                              gb_tile_moden = 
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--                                               
ARRAY_MODE(ARRAY_2D_TILED_THICK) |
--                                               PIPE_CONFIG(ADDR_SURF_P2) |
-                                                
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--                                               NUM_BANKS(ADDR_SURF_16_BANK) |
--                                               
TILE_SPLIT(split_equal_to_row_size));
-+                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 21:
--                              gb_tile_moden = 
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--                                               
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--                                               PIPE_CONFIG(ADDR_SURF_P2) |
-+                              gb_tile_moden = 
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+                                               
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-+                                               
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-+                                               NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-                                                
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--                                               NUM_BANKS(ADDR_SURF_8_BANK));
-+                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 22:
--                              gb_tile_moden = 
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--                                               
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--                                               PIPE_CONFIG(ADDR_SURF_P2) |
-+                              gb_tile_moden = 
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+                                               
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-+                                               
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
--                                               
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
--                                               
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--                                               NUM_BANKS(ADDR_SURF_8_BANK));
-+                                               NUM_BANKS(ADDR_SURF_16_BANK) |
-+                                               
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+                                               
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
-                               break;
-                       case 23:
--                              gb_tile_moden = 
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--                                               
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--                                               PIPE_CONFIG(ADDR_SURF_P2) |
-+                              gb_tile_moden = 
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+                                               
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-+                                               
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-+                                               NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--                                               NUM_BANKS(ADDR_SURF_8_BANK));
-+                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 24:
--                              gb_tile_moden = 
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--                                               
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--                                               PIPE_CONFIG(ADDR_SURF_P2) |
-+                              gb_tile_moden = 
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+                                               
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-+                                               
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-+                                               NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--                                               NUM_BANKS(ADDR_SURF_8_BANK));
-+                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 25:
--                              gb_tile_moden = 
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--                                               
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--                                               PIPE_CONFIG(ADDR_SURF_P2) |
-+                              gb_tile_moden = 
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+                                               
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-+                                               
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
--                                               
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--                                               
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--                                               NUM_BANKS(ADDR_SURF_4_BANK));
--                              break;
--                      case 26:
--                              gb_tile_moden = 
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--                                               
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--                                               PIPE_CONFIG(ADDR_SURF_P2) |
--                                               
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
--                                               
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--                                               
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--                                               NUM_BANKS(ADDR_SURF_4_BANK));
--                              break;
--                      case 27:
--                              gb_tile_moden = 
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--                                               
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--                                               PIPE_CONFIG(ADDR_SURF_P2) |
--                                               
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
--                                               
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--                                               
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--                                               NUM_BANKS(ADDR_SURF_4_BANK));
--                              break;
--                      case 28:
--                              gb_tile_moden = 
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--                                               
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--                                               PIPE_CONFIG(ADDR_SURF_P2) |
--                                               
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
--                                               
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--                                               
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--                                               NUM_BANKS(ADDR_SURF_4_BANK));
--                              break;
--                      case 29:
--                              gb_tile_moden = 
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--                                               
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--                                               PIPE_CONFIG(ADDR_SURF_P2) |
--                                               
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
--                                               
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--                                               
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--                                               NUM_BANKS(ADDR_SURF_4_BANK));
--                              break;
--                      case 30:
--                              gb_tile_moden = 
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--                                               
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--                                               PIPE_CONFIG(ADDR_SURF_P2) |
--                                               
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+                                               NUM_BANKS(ADDR_SURF_8_BANK) |
-                                                
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--                                               NUM_BANKS(ADDR_SURF_4_BANK));
-+                                               
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
-                               break;
-                       default:
--                              continue;
-+                              gb_tile_moden = 0;
-+                              break;
-                       }
-                       adev->gfx.config.tile_mode_array[reg_offset] = 
gb_tile_moden;
-                       WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' 
'--exclude=.svnignore' 
old/patches.fixes/tty-n_hdlc-get-rid-of-racy-n_hdlc.tbuf.patch 
new/patches.fixes/tty-n_hdlc-get-rid-of-racy-n_hdlc.tbuf.patch
--- old/patches.fixes/tty-n_hdlc-get-rid-of-racy-n_hdlc.tbuf.patch      
2017-03-09 17:48:39.000000000 +0100
+++ new/patches.fixes/tty-n_hdlc-get-rid-of-racy-n_hdlc.tbuf.patch      
1970-01-01 01:00:00.000000000 +0100
@@ -1,312 +0,0 @@
-From: Alexander Popov <[email protected]>
-Date: Tue, 28 Feb 2017 19:54:40 +0300
-Subject: tty: n_hdlc: get rid of racy n_hdlc.tbuf
-Patch-mainline: v4.11-rc2
-Git-commit: 82f2341c94d270421f383641b7cd670e474db56b
-Git-tree: https://git.kernel.org/cgit/linux/kernel/git/gregkh/tty.git
-References: bnc#1027565 CVE-2017-2636
-
-Currently N_HDLC line discipline uses a self-made singly linked list for
-data buffers and has n_hdlc.tbuf pointer for buffer retransmitting after
-an error.
-
-The commit be10eb7589337e5defbe214dae038a53dd21add8
-("tty: n_hdlc add buffer flushing") introduced racy access to n_hdlc.tbuf.
-After tx error concurrent flush_tx_queue() and n_hdlc_send_frames() can put
-one data buffer to tx_free_buf_list twice. That causes double free in
-n_hdlc_release().
-
-Let's use standard kernel linked list and get rid of n_hdlc.tbuf:
-in case of tx error put current data buffer after the head of tx_buf_list.
-
-Signed-off-by: Alexander Popov <[email protected]>
-Cc: stable <[email protected]>
-Signed-off-by: Greg Kroah-Hartman <[email protected]>
-Signed-off-by: Jiri Slaby <[email protected]>
----
- drivers/tty/n_hdlc.c |  132 
++++++++++++++++++++++++++-------------------------
- 1 file changed, 69 insertions(+), 63 deletions(-)
-
---- a/drivers/tty/n_hdlc.c
-+++ b/drivers/tty/n_hdlc.c
-@@ -114,7 +114,7 @@
- #define DEFAULT_TX_BUF_COUNT 3
- 
- struct n_hdlc_buf {
--      struct n_hdlc_buf *link;
-+      struct list_head  list_item;
-       int               count;
-       char              buf[1];
- };
-@@ -122,8 +122,7 @@ struct n_hdlc_buf {
- #define       N_HDLC_BUF_SIZE (sizeof(struct n_hdlc_buf) + maxframe)
- 
- struct n_hdlc_buf_list {
--      struct n_hdlc_buf *head;
--      struct n_hdlc_buf *tail;
-+      struct list_head  list;
-       int               count;
-       spinlock_t        spinlock;
- };
-@@ -136,7 +135,6 @@ struct n_hdlc_buf_list {
-  * @backup_tty - TTY to use if tty gets closed
-  * @tbusy - reentrancy flag for tx wakeup code
-  * @woke_up - FIXME: describe this field
-- * @tbuf - currently transmitting tx buffer
-  * @tx_buf_list - list of pending transmit frame buffers
-  * @rx_buf_list - list of received frame buffers
-  * @tx_free_buf_list - list unused transmit frame buffers
-@@ -149,7 +147,6 @@ struct n_hdlc {
-       struct tty_struct       *backup_tty;
-       int                     tbusy;
-       int                     woke_up;
--      struct n_hdlc_buf       *tbuf;
-       struct n_hdlc_buf_list  tx_buf_list;
-       struct n_hdlc_buf_list  rx_buf_list;
-       struct n_hdlc_buf_list  tx_free_buf_list;
-@@ -159,6 +156,8 @@ struct n_hdlc {
- /*
-  * HDLC buffer list manipulation functions
-  */
-+static void n_hdlc_buf_return(struct n_hdlc_buf_list *buf_list,
-+                                              struct n_hdlc_buf *buf);
- static void n_hdlc_buf_put(struct n_hdlc_buf_list *list,
-                          struct n_hdlc_buf *buf);
- static struct n_hdlc_buf *n_hdlc_buf_get(struct n_hdlc_buf_list *list);
-@@ -208,16 +207,9 @@ static void flush_tx_queue(struct tty_st
- {
-       struct n_hdlc *n_hdlc = tty2n_hdlc(tty);
-       struct n_hdlc_buf *buf;
--      unsigned long flags;
- 
-       while ((buf = n_hdlc_buf_get(&n_hdlc->tx_buf_list)))
-               n_hdlc_buf_put(&n_hdlc->tx_free_buf_list, buf);
--      spin_lock_irqsave(&n_hdlc->tx_buf_list.spinlock, flags);
--      if (n_hdlc->tbuf) {
--              n_hdlc_buf_put(&n_hdlc->tx_free_buf_list, n_hdlc->tbuf);
--              n_hdlc->tbuf = NULL;
--      }
--      spin_unlock_irqrestore(&n_hdlc->tx_buf_list.spinlock, flags);
- }
- 
- static struct tty_ldisc_ops n_hdlc_ldisc = {
-@@ -283,7 +275,6 @@ static void n_hdlc_release(struct n_hdlc
-               } else
-                       break;
-       }
--      kfree(n_hdlc->tbuf);
-       kfree(n_hdlc);
-       
- }     /* end of n_hdlc_release() */
-@@ -402,13 +393,7 @@ static void n_hdlc_send_frames(struct n_
-       n_hdlc->woke_up = 0;
-       spin_unlock_irqrestore(&n_hdlc->tx_buf_list.spinlock, flags);
- 
--      /* get current transmit buffer or get new transmit */
--      /* buffer from list of pending transmit buffers */
--              
--      tbuf = n_hdlc->tbuf;
--      if (!tbuf)
--              tbuf = n_hdlc_buf_get(&n_hdlc->tx_buf_list);
--              
-+      tbuf = n_hdlc_buf_get(&n_hdlc->tx_buf_list);
-       while (tbuf) {
-               if (debuglevel >= DEBUG_LEVEL_INFO)     
-                       printk("%s(%d)sending frame %p, count=%d\n",
-@@ -420,7 +405,7 @@ static void n_hdlc_send_frames(struct n_
- 
-               /* rollback was possible and has been done */
-               if (actual == -ERESTARTSYS) {
--                      n_hdlc->tbuf = tbuf;
-+                      n_hdlc_buf_return(&n_hdlc->tx_buf_list, tbuf);
-                       break;
-               }
-               /* if transmit error, throw frame away by */
-@@ -435,10 +420,7 @@ static void n_hdlc_send_frames(struct n_
-                                       
-                       /* free current transmit buffer */
-                       n_hdlc_buf_put(&n_hdlc->tx_free_buf_list, tbuf);
--                      
--                      /* this tx buffer is done */
--                      n_hdlc->tbuf = NULL;
--                      
-+
-                       /* wait up sleeping writers */
-                       wake_up_interruptible(&tty->write_wait);
-       
-@@ -448,10 +430,12 @@ static void n_hdlc_send_frames(struct n_
-                       if (debuglevel >= DEBUG_LEVEL_INFO)     
-                               printk("%s(%d)frame %p pending\n",
-                                       __FILE__,__LINE__,tbuf);
--                                      
--                      /* buffer not accepted by driver */
--                      /* set this buffer as pending buffer */
--                      n_hdlc->tbuf = tbuf;
-+
-+                      /*
-+                       * the buffer was not accepted by driver,
-+                       * return it back into tx queue
-+                       */
-+                      n_hdlc_buf_return(&n_hdlc->tx_buf_list, tbuf);
-                       break;
-               }
-       }
-@@ -749,7 +733,8 @@ static int n_hdlc_tty_ioctl(struct tty_s
-       int error = 0;
-       int count;
-       unsigned long flags;
--      
-+      struct n_hdlc_buf *buf = NULL;
-+
-       if (debuglevel >= DEBUG_LEVEL_INFO)     
-               printk("%s(%d)n_hdlc_tty_ioctl() called %d\n",
-                       __FILE__,__LINE__,cmd);
-@@ -763,8 +748,10 @@ static int n_hdlc_tty_ioctl(struct tty_s
-               /* report count of read data available */
-               /* in next available frame (if any) */
-               spin_lock_irqsave(&n_hdlc->rx_buf_list.spinlock,flags);
--              if (n_hdlc->rx_buf_list.head)
--                      count = n_hdlc->rx_buf_list.head->count;
-+              buf = list_first_entry_or_null(&n_hdlc->rx_buf_list.list,
-+                                              struct n_hdlc_buf, list_item);
-+              if (buf)
-+                      count = buf->count;
-               else
-                       count = 0;
-               spin_unlock_irqrestore(&n_hdlc->rx_buf_list.spinlock,flags);
-@@ -776,8 +763,10 @@ static int n_hdlc_tty_ioctl(struct tty_s
-               count = tty_chars_in_buffer(tty);
-               /* add size of next output frame in queue */
-               spin_lock_irqsave(&n_hdlc->tx_buf_list.spinlock,flags);
--              if (n_hdlc->tx_buf_list.head)
--                      count += n_hdlc->tx_buf_list.head->count;
-+              buf = list_first_entry_or_null(&n_hdlc->tx_buf_list.list,
-+                                              struct n_hdlc_buf, list_item);
-+              if (buf)
-+                      count += buf->count;
-               spin_unlock_irqrestore(&n_hdlc->tx_buf_list.spinlock,flags);
-               error = put_user(count, (int __user *)arg);
-               break;
-@@ -825,14 +814,14 @@ static unsigned int n_hdlc_tty_poll(stru
-               poll_wait(filp, &tty->write_wait, wait);
- 
-               /* set bits for operations that won't block */
--              if (n_hdlc->rx_buf_list.head)
-+              if (!list_empty(&n_hdlc->rx_buf_list.list))
-                       mask |= POLLIN | POLLRDNORM;    /* readable */
-               if (test_bit(TTY_OTHER_CLOSED, &tty->flags))
-                       mask |= POLLHUP;
-               if (tty_hung_up_p(filp))
-                       mask |= POLLHUP;
-               if (!tty_is_writelocked(tty) &&
--                              n_hdlc->tx_free_buf_list.head)
-+                              !list_empty(&n_hdlc->tx_free_buf_list.list))
-                       mask |= POLLOUT | POLLWRNORM;   /* writable */
-       }
-       return mask;
-@@ -856,7 +845,12 @@ static struct n_hdlc *n_hdlc_alloc(void)
-       spin_lock_init(&n_hdlc->tx_free_buf_list.spinlock);
-       spin_lock_init(&n_hdlc->rx_buf_list.spinlock);
-       spin_lock_init(&n_hdlc->tx_buf_list.spinlock);
--      
-+
-+      INIT_LIST_HEAD(&n_hdlc->rx_free_buf_list.list);
-+      INIT_LIST_HEAD(&n_hdlc->tx_free_buf_list.list);
-+      INIT_LIST_HEAD(&n_hdlc->rx_buf_list.list);
-+      INIT_LIST_HEAD(&n_hdlc->tx_buf_list.list);
-+
-       /* allocate free rx buffer list */
-       for(i=0;i<DEFAULT_RX_BUF_COUNT;i++) {
-               buf = kmalloc(N_HDLC_BUF_SIZE, GFP_KERNEL);
-@@ -884,53 +878,65 @@ static struct n_hdlc *n_hdlc_alloc(void)
- }     /* end of n_hdlc_alloc() */
- 
- /**
-+ * n_hdlc_buf_return - put the HDLC buffer after the head of the specified 
list
-+ * @buf_list - pointer to the buffer list
-+ * @buf - pointer to the buffer
-+ */
-+static void n_hdlc_buf_return(struct n_hdlc_buf_list *buf_list,
-+                                              struct n_hdlc_buf *buf)
-+{
-+      unsigned long flags;
-+
-+      spin_lock_irqsave(&buf_list->spinlock, flags);
-+
-+      list_add(&buf->list_item, &buf_list->list);
-+      buf_list->count++;
-+
-+      spin_unlock_irqrestore(&buf_list->spinlock, flags);
-+}
-+
-+/**
-  * n_hdlc_buf_put - add specified HDLC buffer to tail of specified list
-- * @list - pointer to buffer list
-+ * @buf_list - pointer to buffer list
-  * @buf       - pointer to buffer
-  */
--static void n_hdlc_buf_put(struct n_hdlc_buf_list *list,
-+static void n_hdlc_buf_put(struct n_hdlc_buf_list *buf_list,
-                          struct n_hdlc_buf *buf)
- {
-       unsigned long flags;
--      spin_lock_irqsave(&list->spinlock,flags);
--      
--      buf->link=NULL;
--      if (list->tail)
--              list->tail->link = buf;
--      else
--              list->head = buf;
--      list->tail = buf;
--      (list->count)++;
--      
--      spin_unlock_irqrestore(&list->spinlock,flags);
--      
-+
-+      spin_lock_irqsave(&buf_list->spinlock, flags);
-+
-+      list_add_tail(&buf->list_item, &buf_list->list);
-+      buf_list->count++;
-+
-+      spin_unlock_irqrestore(&buf_list->spinlock, flags);
- }     /* end of n_hdlc_buf_put() */
- 
- /**
-  * n_hdlc_buf_get - remove and return an HDLC buffer from list
-- * @list - pointer to HDLC buffer list
-+ * @buf_list - pointer to HDLC buffer list
-  * 
-  * Remove and return an HDLC buffer from the head of the specified HDLC buffer
-  * list.
-  * Returns a pointer to HDLC buffer if available, otherwise %NULL.
-  */
--static struct n_hdlc_buf* n_hdlc_buf_get(struct n_hdlc_buf_list *list)
-+static struct n_hdlc_buf *n_hdlc_buf_get(struct n_hdlc_buf_list *buf_list)
- {
-       unsigned long flags;
-       struct n_hdlc_buf *buf;
--      spin_lock_irqsave(&list->spinlock,flags);
--      
--      buf = list->head;
-+
-+      spin_lock_irqsave(&buf_list->spinlock, flags);
-+
-+      buf = list_first_entry_or_null(&buf_list->list,
-+                                              struct n_hdlc_buf, list_item);
-       if (buf) {
--              list->head = buf->link;
--              (list->count)--;
-+              list_del(&buf->list_item);
-+              buf_list->count--;
-       }
--      if (!list->head)
--              list->tail = NULL;
--      
--      spin_unlock_irqrestore(&list->spinlock,flags);
-+
-+      spin_unlock_irqrestore(&buf_list->spinlock, flags);
-       return buf;
--      
- }     /* end of n_hdlc_buf_get() */
- 
- static char hdlc_banner[] __initdata =

++++++ patches.kernel.org.tar.bz2 ++++++
++++ 3998 lines of diff (skipped)

++++++ series.conf ++++++
--- /var/tmp/diff_new_pack.DznNGi/_old  2017-03-16 09:33:12.133546983 +0100
+++ /var/tmp/diff_new_pack.DznNGi/_new  2017-03-16 09:33:12.137546417 +0100
@@ -29,6 +29,7 @@
        ########################################################
        patches.kernel.org/patch-4.10.1
        patches.kernel.org/patch-4.10.1-2
+       patches.kernel.org/patch-4.10.2-3
 
        ########################################################
        # Build fixes that apply to the vanilla kernel too.
@@ -320,7 +321,6 @@
        patches.fixes/drm-i915-Fix-S4-resume-breakage
        patches.drivers/drm-reference-count-event-completion
        patches.fixes/drm-i915-gvt-Fix-superfluous-newline-in-GVT_DISPLAY_
-       patches.fixes/drm-amdgpu-revert-update-tile-table-for-oland-hainan.patch
 
        ########################################################
        # video4linux
@@ -375,7 +375,6 @@
        # Char / serial
        ########################################################
        patches.drivers/fbcon-Fix-vc-attr-at-deinit
-       patches.fixes/tty-n_hdlc-get-rid-of-racy-n_hdlc.tbuf.patch
 
        ########################################################
        # Other driver fixes

++++++ source-timestamp ++++++
--- /var/tmp/diff_new_pack.DznNGi/_old  2017-03-16 09:33:12.177540754 +0100
+++ /var/tmp/diff_new_pack.DznNGi/_new  2017-03-16 09:33:12.181540187 +0100
@@ -1,3 +1,3 @@
-2017-03-12 20:54:41 +0100
-GIT Revision: bfb2d2236a4d00f925d24a4a4d1c200a43c2bc34
+2017-03-15 08:47:00 +0100
+GIT Revision: 0c9f8e4b1773b1b69ff084b1ce5e5d21e868aa67
 GIT Branch: stable


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