Hello community, here is the log from the commit of package verilator for openSUSE:Factory checked in at 2017-03-17 15:07:30 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/verilator (Old) and /work/SRC/openSUSE:Factory/.verilator.new (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "verilator" Fri Mar 17 15:07:30 2017 rev:3 rq:480622 version:3.900 Changes: -------- --- /work/SRC/openSUSE:Factory/verilator/verilator.changes 2017-03-02 19:25:23.477044451 +0100 +++ /work/SRC/openSUSE:Factory/.verilator.new/verilator.changes 2017-03-17 15:07:32.017488368 +0100 @@ -1,0 +2,5 @@ +Thu Feb 16 10:56:03 UTC 2017 - [email protected] + +- Rewrite description to give more insight as to what it does. + +------------------------------------------------------------------- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ verilator.spec ++++++ --- /var/tmp/diff_new_pack.vgtpcG/_old 2017-03-17 15:07:33.233316777 +0100 +++ /var/tmp/diff_new_pack.vgtpcG/_new 2017-03-17 15:07:33.237316212 +0100 @@ -19,7 +19,7 @@ Name: verilator Version: 3.900 Release: 0 -Summary: A fast simulator for synthesizable Verilog +Summary: Compiling Verilog HDL simulator License: Artistic-2.0 or LGPL-3.0 Group: Productivity/Scientific/Electronics Url: https://www.veripool.org/projects/verilator/wiki/Intro @@ -34,12 +34,10 @@ BuildRoot: %{_tmppath}/%{name}-%{version}-build %description -Verilator is the fastest free Verilog HDL simulator, and beats most -commercial simulators. It compiles synthesizable Verilog (not test-bench -code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ -or SystemC code. It is designed for large projects where fast simulation -performance is of primary concern, and is especially well suited to -generate executable models of CPUs for embedded software design teams. +Verilator compiles synthesizable Verilog (not test-bench code), plus +some PSL, SystemVerilog and Synthesis assertions into an optimized +model which is in turn wrapped inside a C++/SystemC module for faster +execution. %package doc Summary: Documentation for verilator in HTML format @@ -48,7 +46,7 @@ BuildArch: noarch %description doc -Verilator is the fastest free Verilog HDL simulator. +Verilator is a compiling Verilog HDL simulator. This package contains documentation for verilator in HTML format. @@ -59,7 +57,7 @@ BuildArch: noarch %description doc-pdf -Verilator is the fastest free Verilog HDL simulator. +Verilator is a compiling Verilog HDL simulator. This package contains documentation for verilator in PDF format. @@ -70,7 +68,7 @@ BuildArch: noarch %description examples -Verilator is the fastest free Verilog HDL simulator. +Verilator is a compiling Verilog HDL simulator. This package contains examples of using verilator.
