Hello community,
here is the log from the commit of package kernel-source for openSUSE:Factory
checked in at 2017-09-23 21:32:26
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Comparing /work/SRC/openSUSE:Factory/kernel-source (Old)
and /work/SRC/openSUSE:Factory/.kernel-source.new (New)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "kernel-source"
Sat Sep 23 21:32:26 2017 rev:380 rq:527460 version:4.13.3
Changes:
--------
--- /work/SRC/openSUSE:Factory/kernel-source/dtb-aarch64.changes
2017-09-17 22:27:09.302914462 +0200
+++ /work/SRC/openSUSE:Factory/.kernel-source.new/dtb-aarch64.changes
2017-09-23 21:32:31.896625186 +0200
@@ -1,0 +2,41 @@
+Wed Sep 20 08:43:24 CEST 2017 - jsl...@suse.cz
+
+- Linux 4.13.3 (bnc#1012628).
+- Refresh
+ patches.suse/0001-x86-entry-64-Refactor-IRQ-stacks-and-make-them-NMI-s.patch.
+- commit 76ecbd3
+
+-------------------------------------------------------------------
+Tue Sep 19 08:45:19 CEST 2017 - jsl...@suse.cz
+
+- Refresh
+ patches.suse/0001-objtool-Don-t-report-end-of-section-error-after-an-e.patch.
+- Refresh
+ patches.suse/0002-x86-head-Remove-confusing-comment.patch.
+- Refresh
+ patches.suse/0003-x86-head-Remove-unused-bad_address-code.patch.
+- Refresh
+ patches.suse/0004-x86-head-Fix-head-ELF-function-annotations.patch.
+- Refresh
+ patches.suse/0005-x86-boot-Annotate-verify_cpu-as-a-callable-function.patch.
+- Refresh
+ patches.suse/0006-x86-xen-Fix-xen-head-ELF-annotations.patch.
+- Refresh
+ patches.suse/0007-x86-xen-Add-unwind-hint-annotations.patch.
+- Refresh
+ patches.suse/0008-x86-head-Add-unwind-hint-annotations.patch.
+- Delete
+ patches.suse/0007-x86-xen-Add-unwind-hint-annotations-fix.patch.
+ Update to the submitted v2.
+- commit 27de3c0
+
+-------------------------------------------------------------------
+Sun Sep 17 14:41:51 CEST 2017 - jdelv...@suse.de
+
+- drm/amdgpu: revert tile table update for oland (boo#1027378,
+ boo#1039806, bko#194761).
+- Delete
+ patches.fixes/drm-amdgpu-revert-update-tile-table-for-oland-hainan.patch.
+- commit 51745cf
+
+-------------------------------------------------------------------
@@ -11,0 +53,6 @@
+Wed Sep 13 20:50:54 CEST 2017 - ti...@suse.de
+
+- rpm/kernel-docs.spec.in: Fix a thinko for xmlto buildreq condition
+- commit 0ef59d3
+
+-------------------------------------------------------------------
@@ -22,0 +70,6 @@
+
+-------------------------------------------------------------------
+Tue Sep 12 13:54:48 CEST 2017 - msucha...@suse.de
+
+- rpm/kernel-docs.spec.in: make unpack scripts executable
+- commit 1ba3766
dtb-armv6l.changes: same change
dtb-armv7l.changes: same change
kernel-64kb.changes: same change
kernel-debug.changes: same change
kernel-default.changes: same change
kernel-docs.changes: same change
kernel-lpae.changes: same change
kernel-obs-build.changes: same change
kernel-obs-qa.changes: same change
kernel-pae.changes: same change
kernel-source.changes: same change
kernel-syms.changes: same change
kernel-syzkaller.changes: same change
kernel-vanilla.changes: same change
kernel-zfcpdump.changes: same change
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Other differences:
------------------
++++++ dtb-aarch64.spec ++++++
--- /var/tmp/diff_new_pack.cuPo9w/_old 2017-09-23 21:32:39.219594946 +0200
+++ /var/tmp/diff_new_pack.cuPo9w/_new 2017-09-23 21:32:39.219594946 +0200
@@ -17,7 +17,7 @@
%define srcversion 4.13
-%define patchversion 4.13.2
+%define patchversion 4.13.3
%define variant %{nil}
%include %_sourcedir/kernel-spec-macros
@@ -29,9 +29,9 @@
%(chmod +x
%_sourcedir/{guards,apply-patches,check-for-config-changes,group-source-files.pl,split-modules,modversions,kabi.pl,mkspec,compute-PATCHVERSION.sh,arch-symbols,log.sh,try-disable-staging-driver,compress-vmlinux.sh,mkspec-dtb})
Name: dtb-aarch64
-Version: 4.13.2
+Version: 4.13.3
%if 0%{?is_kotd}
-Release: <RELEASE>.g68f4aee
+Release: <RELEASE>.g76ecbd3
%else
Release: 0
%endif
dtb-armv6l.spec: same change
dtb-armv7l.spec: same change
++++++ kernel-64kb.spec ++++++
--- /var/tmp/diff_new_pack.cuPo9w/_old 2017-09-23 21:32:39.303583130 +0200
+++ /var/tmp/diff_new_pack.cuPo9w/_new 2017-09-23 21:32:39.307582568 +0200
@@ -18,7 +18,7 @@
%define srcversion 4.13
-%define patchversion 4.13.2
+%define patchversion 4.13.3
%define variant %{nil}
%define vanilla_only 0
@@ -58,9 +58,9 @@
Summary: Kernel with 64kb PAGE_SIZE
License: GPL-2.0
Group: System/Kernel
-Version: 4.13.2
+Version: 4.13.3
%if 0%{?is_kotd}
-Release: <RELEASE>.g68f4aee
+Release: <RELEASE>.g76ecbd3
%else
Release: 0
%endif
kernel-debug.spec: same change
kernel-default.spec: same change
++++++ kernel-docs.spec ++++++
--- /var/tmp/diff_new_pack.cuPo9w/_old 2017-09-23 21:32:39.379572440 +0200
+++ /var/tmp/diff_new_pack.cuPo9w/_new 2017-09-23 21:32:39.383571877 +0200
@@ -17,7 +17,7 @@
%define srcversion 4.13
-%define patchversion 4.13.2
+%define patchversion 4.13.3
%define variant %{nil}
%include %_sourcedir/kernel-spec-macros
@@ -31,14 +31,14 @@
Summary: Kernel Documentation
License: GPL-2.0
Group: Documentation/Man
-Version: 4.13.2
+Version: 4.13.3
%if 0%{?is_kotd}
-Release: <RELEASE>.g68f4aee
+Release: <RELEASE>.g76ecbd3
%else
Release: 0
%endif
# TW (4.13 or later) no longer needs xmlto
-%if !0%{?sle_version}
+%if 0%{?sle_version}
BuildRequires: xmlto
%endif
%if %build_pdf || %build_html
++++++ kernel-lpae.spec ++++++
--- /var/tmp/diff_new_pack.cuPo9w/_old 2017-09-23 21:32:39.407568501 +0200
+++ /var/tmp/diff_new_pack.cuPo9w/_new 2017-09-23 21:32:39.411567938 +0200
@@ -18,7 +18,7 @@
%define srcversion 4.13
-%define patchversion 4.13.2
+%define patchversion 4.13.3
%define variant %{nil}
%define vanilla_only 0
@@ -58,9 +58,9 @@
Summary: Kernel for LPAE enabled systems
License: GPL-2.0
Group: System/Kernel
-Version: 4.13.2
+Version: 4.13.3
%if 0%{?is_kotd}
-Release: <RELEASE>.g68f4aee
+Release: <RELEASE>.g76ecbd3
%else
Release: 0
%endif
++++++ kernel-obs-build.spec ++++++
--- /var/tmp/diff_new_pack.cuPo9w/_old 2017-09-23 21:32:39.443563437 +0200
+++ /var/tmp/diff_new_pack.cuPo9w/_new 2017-09-23 21:32:39.443563437 +0200
@@ -19,7 +19,7 @@
#!BuildIgnore: post-build-checks
-%define patchversion 4.13.2
+%define patchversion 4.13.3
%define variant %{nil}
%define vanilla_only 0
@@ -57,9 +57,9 @@
Summary: package kernel and initrd for OBS VM builds
License: GPL-2.0
Group: SLES
-Version: 4.13.2
+Version: 4.13.3
%if 0%{?is_kotd}
-Release: <RELEASE>.g68f4aee
+Release: <RELEASE>.g76ecbd3
%else
Release: 0
%endif
++++++ kernel-obs-qa.spec ++++++
--- /var/tmp/diff_new_pack.cuPo9w/_old 2017-09-23 21:32:39.471559498 +0200
+++ /var/tmp/diff_new_pack.cuPo9w/_new 2017-09-23 21:32:39.475558936 +0200
@@ -17,7 +17,7 @@
# needsrootforbuild
-%define patchversion 4.13.2
+%define patchversion 4.13.3
%define variant %{nil}
%include %_sourcedir/kernel-spec-macros
@@ -36,9 +36,9 @@
Summary: Basic QA tests for the kernel
License: GPL-2.0
Group: SLES
-Version: 4.13.2
+Version: 4.13.3
%if 0%{?is_kotd}
-Release: <RELEASE>.g68f4aee
+Release: <RELEASE>.g76ecbd3
%else
Release: 0
%endif
++++++ kernel-pae.spec ++++++
--- /var/tmp/diff_new_pack.cuPo9w/_old 2017-09-23 21:32:39.499555560 +0200
+++ /var/tmp/diff_new_pack.cuPo9w/_new 2017-09-23 21:32:39.499555560 +0200
@@ -18,7 +18,7 @@
%define srcversion 4.13
-%define patchversion 4.13.2
+%define patchversion 4.13.3
%define variant %{nil}
%define vanilla_only 0
@@ -58,9 +58,9 @@
Summary: Kernel with PAE Support
License: GPL-2.0
Group: System/Kernel
-Version: 4.13.2
+Version: 4.13.3
%if 0%{?is_kotd}
-Release: <RELEASE>.g68f4aee
+Release: <RELEASE>.g76ecbd3
%else
Release: 0
%endif
++++++ kernel-source.spec ++++++
--- /var/tmp/diff_new_pack.cuPo9w/_old 2017-09-23 21:32:39.519552746 +0200
+++ /var/tmp/diff_new_pack.cuPo9w/_new 2017-09-23 21:32:39.523552184 +0200
@@ -18,7 +18,7 @@
%define srcversion 4.13
-%define patchversion 4.13.2
+%define patchversion 4.13.3
%define variant %{nil}
%define vanilla_only 0
@@ -30,9 +30,9 @@
Summary: The Linux Kernel Sources
License: GPL-2.0
Group: Development/Sources
-Version: 4.13.2
+Version: 4.13.3
%if 0%{?is_kotd}
-Release: <RELEASE>.g68f4aee
+Release: <RELEASE>.g76ecbd3
%else
Release: 0
%endif
++++++ kernel-syms.spec ++++++
--- /var/tmp/diff_new_pack.cuPo9w/_old 2017-09-23 21:32:39.543549370 +0200
+++ /var/tmp/diff_new_pack.cuPo9w/_new 2017-09-23 21:32:39.547548808 +0200
@@ -24,10 +24,10 @@
Summary: Kernel Symbol Versions (modversions)
License: GPL-2.0
Group: Development/Sources
-Version: 4.13.2
+Version: 4.13.3
%if %using_buildservice
%if 0%{?is_kotd}
-Release: <RELEASE>.g68f4aee
+Release: <RELEASE>.g76ecbd3
%else
Release: 0
%endif
++++++ kernel-syzkaller.spec ++++++
--- /var/tmp/diff_new_pack.cuPo9w/_old 2017-09-23 21:32:39.575544869 +0200
+++ /var/tmp/diff_new_pack.cuPo9w/_new 2017-09-23 21:32:39.579544307 +0200
@@ -18,7 +18,7 @@
%define srcversion 4.13
-%define patchversion 4.13.2
+%define patchversion 4.13.3
%define variant %{nil}
%define vanilla_only 0
@@ -58,9 +58,9 @@
Summary: Kernel used for fuzzing by syzkaller
License: GPL-2.0
Group: System/Kernel
-Version: 4.13.2
+Version: 4.13.3
%if 0%{?is_kotd}
-Release: <RELEASE>.g68f4aee
+Release: <RELEASE>.g76ecbd3
%else
Release: 0
%endif
kernel-vanilla.spec: same change
kernel-zfcpdump.spec: same change
++++++ kernel-docs.spec.in ++++++
--- /var/tmp/diff_new_pack.cuPo9w/_old 2017-09-23 21:32:40.067475661 +0200
+++ /var/tmp/diff_new_pack.cuPo9w/_new 2017-09-23 21:32:40.067475661 +0200
@@ -38,7 +38,7 @@
Release: @RELEASE@
%endif
# TW (4.13 or later) no longer needs xmlto
-%if !0%{?sle_version}
+%if 0%{?sle_version}
BuildRequires: xmlto
%endif
%if %build_pdf || %build_html
++++++ patches.fixes.tar.bz2 ++++++
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/patches.fixes/drm-amdgpu-revert-update-tile-table-for-oland-hainan.patch
new/patches.fixes/drm-amdgpu-revert-update-tile-table-for-oland-hainan.patch
---
old/patches.fixes/drm-amdgpu-revert-update-tile-table-for-oland-hainan.patch
2017-09-14 20:35:54.000000000 +0200
+++
new/patches.fixes/drm-amdgpu-revert-update-tile-table-for-oland-hainan.patch
1970-01-01 01:00:00.000000000 +0100
@@ -1,454 +0,0 @@
-From: Jean Delvare <jdelv...@suse.de>
-Subject: Revert "drm/amdgpu: update tile table for oland/hainan"
-References: boo#1027378, boo#1039806
-Patch-mainline: Not yet, will send later today
-
-Revert commit f8d9422ef80c ("drm/amdgpu: update tile table for
-oland/hainan") as it is causing ugly visual artefacts on at least
-Oland. This is only an optimization so we can live without it.
-
-This fixes kernel bug #194761:
-amdgpu driver breaks on Oland (SI)
-https://bugzilla.kernel.org/show_bug.cgi?id=194761
-
-Signed-off-by: Jean Delvare <jdelv...@suse.de>
-Fixes: f8d9422ef80c ("drm/amdgpu: update tile table for oland/hainan")
-Acked-by: Alex Deucher <alexander.deuc...@amd.com>
-Cc: Flora Cui <flora....@amd.com>
-Cc: Junwei Zhang <jerry.zh...@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 330
++++++++++++++--------------------
- 1 file changed, 139 insertions(+), 191 deletions(-)
-
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
-@@ -708,290 +708,238 @@ static void gfx_v6_0_tiling_mode_table_i
- for (reg_offset = 0; reg_offset < num_tile_mode_states;
reg_offset++) {
- switch (reg_offset) {
- case 0:
-- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
--
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-+ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-+ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-+ NUM_BANKS(ADDR_SURF_16_BANK) |
-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
- break;
- case 1:
-- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
--
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-+ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-+ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
-+ NUM_BANKS(ADDR_SURF_16_BANK) |
-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
- break;
- case 2:
-- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
--
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-+ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-+ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-+ NUM_BANKS(ADDR_SURF_16_BANK) |
-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
- break;
- case 3:
-- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
--
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-+ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-+ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
-+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
-+ NUM_BANKS(ADDR_SURF_16_BANK) |
-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-- NUM_BANKS(ADDR_SURF_8_BANK) |
--
TILE_SPLIT(split_equal_to_row_size));
-+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
- break;
- case 4:
-- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
--
ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2));
-+ gb_tile_moden =
(ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-+ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
-+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-+ NUM_BANKS(ADDR_SURF_16_BANK) |
-+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 5:
-- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
--
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
--
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-+ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-+ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
-+
TILE_SPLIT(split_equal_to_row_size) |
-+ NUM_BANKS(ADDR_SURF_16_BANK) |
-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 6:
-- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
--
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
--
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-+ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-+ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
-+
TILE_SPLIT(split_equal_to_row_size) |
-+ NUM_BANKS(ADDR_SURF_16_BANK) |
-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 7:
-- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
--
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
--
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
-+ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-+ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
-+
TILE_SPLIT(split_equal_to_row_size) |
-+ NUM_BANKS(ADDR_SURF_16_BANK) |
-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-- NUM_BANKS(ADDR_SURF_4_BANK));
-+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
- break;
- case 8:
-- gb_tile_moden =
(ARRAY_MODE(ARRAY_LINEAR_ALIGNED));
-+ gb_tile_moden =
(ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
-+
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
-+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-+ NUM_BANKS(ADDR_SURF_16_BANK) |
-+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 9:
-- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
--
ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2));
-+ gb_tile_moden =
(ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
-+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-+ NUM_BANKS(ADDR_SURF_16_BANK) |
-+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 10:
-- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
--
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-+ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-+ NUM_BANKS(ADDR_SURF_16_BANK) |
-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
- break;
- case 11:
-- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
--
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-+ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-+ NUM_BANKS(ADDR_SURF_16_BANK) |
-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 12:
-- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
--
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-+ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-+ NUM_BANKS(ADDR_SURF_16_BANK) |
-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 13:
-- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--
ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2));
-+ gb_tile_moden =
(ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-+ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
-+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-+ NUM_BANKS(ADDR_SURF_16_BANK) |
-+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 14:
-- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-+ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-+ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-+ NUM_BANKS(ADDR_SURF_16_BANK) |
-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 15:
-- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-+ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-+ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-+ NUM_BANKS(ADDR_SURF_16_BANK) |
-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 16:
-- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-+ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-+ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-+ NUM_BANKS(ADDR_SURF_16_BANK) |
-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 17:
-- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
--
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_16_BANK) |
--
TILE_SPLIT(split_equal_to_row_size));
-- break;
-- case 18:
-- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--
ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P2));
-- break;
-- case 19:
-- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--
ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
--
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-+ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
-+
TILE_SPLIT(split_equal_to_row_size) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
--
TILE_SPLIT(split_equal_to_row_size));
-- break;
-- case 20:
-- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--
ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_16_BANK) |
--
TILE_SPLIT(split_equal_to_row_size));
-+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 21:
-- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-+ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-+
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-+ NUM_BANKS(ADDR_SURF_16_BANK) |
-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 22:
-- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-+ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-+
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
--
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
--
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-+ NUM_BANKS(ADDR_SURF_16_BANK) |
-+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
- break;
- case 23:
-- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-+ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-+
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-+ NUM_BANKS(ADDR_SURF_16_BANK) |
-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 24:
-- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-+ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-+
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-+ NUM_BANKS(ADDR_SURF_16_BANK) |
-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 25:
-- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-+ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-+
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
--
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-- NUM_BANKS(ADDR_SURF_4_BANK));
-- break;
-- case 26:
-- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
--
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
--
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-- NUM_BANKS(ADDR_SURF_4_BANK));
-- break;
-- case 27:
-- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
--
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
--
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-- NUM_BANKS(ADDR_SURF_4_BANK));
-- break;
-- case 28:
-- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
--
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
--
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-- NUM_BANKS(ADDR_SURF_4_BANK));
-- break;
-- case 29:
-- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
--
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
--
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-- NUM_BANKS(ADDR_SURF_4_BANK));
-- break;
-- case 30:
-- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
--
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
--
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+ NUM_BANKS(ADDR_SURF_8_BANK) |
-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-- NUM_BANKS(ADDR_SURF_4_BANK));
-+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
- break;
- default:
-- continue;
-+ gb_tile_moden = 0;
-+ break;
- }
- adev->gfx.config.tile_mode_array[reg_offset] =
gb_tile_moden;
- WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/patches.fixes/drm-amdgpu-revert-update-tile-table-for-oland.patch
new/patches.fixes/drm-amdgpu-revert-update-tile-table-for-oland.patch
--- old/patches.fixes/drm-amdgpu-revert-update-tile-table-for-oland.patch
1970-01-01 01:00:00.000000000 +0100
+++ new/patches.fixes/drm-amdgpu-revert-update-tile-table-for-oland.patch
2017-09-19 09:38:28.000000000 +0200
@@ -0,0 +1,233 @@
+From: Jean Delvare <jdelv...@suse.de>
+Subject: drm/amdgpu: revert tile table update for oland
+References: boo#1027378, boo#1039806, bko#194761
+Patch-mainline: Submitted
https://www.spinics.net/lists/dri-devel/msg152025.html
+
+Several users have complained that the tile table update broke Oland
+support. Despite several attempts to fix it, the root cause is still
+unknown at this point and no solution is available. As it is not
+acceptable to leave a known regression breaking a major functionality
+in the kernel for several releases, let's just reverse this
+optimization for now. It can be implemented again later if and only
+if the breakage is understood and fixed.
+
+As there were no complaints for Hainan so far, only the Oland part of
+the offending commit is reverted. Optimization is preserved on
+Hainan, so this commit isn't an actual revert of the original.
+
+This fixes bug #194761:
+https://bugzilla.kernel.org/show_bug.cgi?id=194761
+
+Signed-off-by: Jean Delvare <jdelv...@suse.de>
+Fixes: f8d9422ef80c ("drm/amdgpu: update tile table for oland/hainan")
+Cc: Flora Cui <flora....@amd.com>
+Cc: Junwei Zhang <jerry.zh...@amd.com>
+Cc: Alex Deucher <alexander.deuc...@amd.com>
+Cc: Marek Olšák <mar...@gmail.com>
+---
+This version of the fix is suitable for kernels v4.13 and up.
+I'm running it for some time now it works perfectly on my
+Radeon R5 240 (Dell OEM):
+01:00.0 VGA compatible controller [0300]: Advanced Micro Devices, Inc.
[AMD/ATI] Oland [Radeon HD 8570 / R7 240/340 OEM] [1002:6611]
+
+ drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 189
+++++++++++++++++++++++++++++++++-
+ 1 file changed, 188 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+@@ -636,7 +636,194 @@ static void gfx_v6_0_tiling_mode_table_i
+ NUM_BANKS(ADDR_SURF_2_BANK);
+ for (reg_offset = 0; reg_offset < num_tile_mode_states;
reg_offset++)
+ WREG32(mmGB_TILE_MODE0 + reg_offset,
tilemode[reg_offset]);
+- } else if (adev->asic_type == CHIP_OLAND || adev->asic_type ==
CHIP_HAINAN) {
++ } else if (adev->asic_type == CHIP_OLAND) {
++ tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
++ ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
++ tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
++ ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
++ tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
++ ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
++ tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
++ ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
++ tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
++ ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
++ tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
++ ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
++ TILE_SPLIT(split_equal_to_row_size) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
++ tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
++ ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
++ TILE_SPLIT(split_equal_to_row_size) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
++ tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
++ ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
++ TILE_SPLIT(split_equal_to_row_size) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
++ tilemode[8] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING)
|
++ ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
++ tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING)
|
++ ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
++ tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING)
|
++ ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
++ tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING)
|
++ ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
++ tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING)
|
++ ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
++ tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
++ ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
++ tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
++ ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
++ tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
++ ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
++ tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
++ ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
++ tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
++ ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
++ TILE_SPLIT(split_equal_to_row_size) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
++ tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
++ ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
++ tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
++ ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
++ tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
++ ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
++ tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
++ ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
++ tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
++ ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
++ NUM_BANKS(ADDR_SURF_8_BANK) |
++ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1);
++ for (reg_offset = 0; reg_offset < num_tile_mode_states;
reg_offset++)
++ WREG32(mmGB_TILE_MODE0 + reg_offset,
tilemode[reg_offset]);
++ } else if (adev->asic_type == CHIP_HAINAN) {
+ tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+ ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ PIPE_CONFIG(ADDR_SURF_P2) |
++++++ patches.kernel.org.tar.bz2 ++++++
++++ 2893 lines of diff (skipped)
++++++ patches.suse.tar.bz2 ++++++
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/patches.suse/0001-objtool-Don-t-report-end-of-section-error-after-an-e.patch
new/patches.suse/0001-objtool-Don-t-report-end-of-section-error-after-an-e.patch
---
old/patches.suse/0001-objtool-Don-t-report-end-of-section-error-after-an-e.patch
2017-09-12 14:57:54.000000000 +0200
+++
new/patches.suse/0001-objtool-Don-t-report-end-of-section-error-after-an-e.patch
2017-09-20 08:43:24.000000000 +0200
@@ -1,7 +1,7 @@
From: Josh Poimboeuf <jpoim...@redhat.com>
-Date: Thu, 31 Aug 2017 15:23:39 -0500
+Date: Mon, 18 Sep 2017 21:43:30 -0500
Subject: objtool: Don't report end of section error after an empty unwind hint
-Patch-mainline: submitted on 8/31/2017
+Patch-mainline: submitted on 9/19/2017
References: bnc#1058115
If asm code specifies an UNWIND_HINT_EMPTY hint, don't warn if the
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/patches.suse/0001-x86-entry-64-Refactor-IRQ-stacks-and-make-them-NMI-s.patch
new/patches.suse/0001-x86-entry-64-Refactor-IRQ-stacks-and-make-them-NMI-s.patch
---
old/patches.suse/0001-x86-entry-64-Refactor-IRQ-stacks-and-make-them-NMI-s.patch
2017-09-12 14:57:54.000000000 +0200
+++
new/patches.suse/0001-x86-entry-64-Refactor-IRQ-stacks-and-make-them-NMI-s.patch
2017-09-20 08:43:24.000000000 +0200
@@ -173,9 +173,9 @@
#endif
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
-@@ -279,6 +279,9 @@ __switch_to(struct task_struct *prev_p,
+@@ -404,6 +404,9 @@ __switch_to(struct task_struct *prev_p,
+ int cpu = smp_processor_id();
struct tss_struct *tss = &per_cpu(cpu_tss, cpu);
- unsigned prev_fsindex, prev_gsindex;
+ WARN_ON_ONCE(IS_ENABLED(CONFIG_DEBUG_ENTRY) &&
+ this_cpu_read(irq_count) != -1);
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/patches.suse/0002-x86-head-Remove-confusing-comment.patch
new/patches.suse/0002-x86-head-Remove-confusing-comment.patch
--- old/patches.suse/0002-x86-head-Remove-confusing-comment.patch
2017-09-12 14:57:54.000000000 +0200
+++ new/patches.suse/0002-x86-head-Remove-confusing-comment.patch
2017-09-20 08:43:24.000000000 +0200
@@ -1,7 +1,7 @@
From: Josh Poimboeuf <jpoim...@redhat.com>
-Date: Thu, 31 Aug 2017 15:23:40 -0500
+Date: Mon, 18 Sep 2017 21:43:31 -0500
Subject: x86/head: Remove confusing comment
-Patch-mainline: submitted on 8/31/2017
+Patch-mainline: submitted on 9/19/2017
References: bnc#1058115
This comment is actively wrong and confusing. It refers to the
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/patches.suse/0003-x86-head-Remove-unused-bad_address-code.patch
new/patches.suse/0003-x86-head-Remove-unused-bad_address-code.patch
--- old/patches.suse/0003-x86-head-Remove-unused-bad_address-code.patch
2017-09-12 14:57:54.000000000 +0200
+++ new/patches.suse/0003-x86-head-Remove-unused-bad_address-code.patch
2017-09-20 08:43:24.000000000 +0200
@@ -1,7 +1,7 @@
From: Josh Poimboeuf <jpoim...@redhat.com>
-Date: Thu, 31 Aug 2017 15:23:41 -0500
+Date: Mon, 18 Sep 2017 21:43:32 -0500
Subject: x86/head: Remove unused 'bad_address' code
-Patch-mainline: submitted on 8/31/2017
+Patch-mainline: submitted on 9/19/2017
References: bnc#1058115
It's no longer possible for this code to be executed, so remove it.
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/patches.suse/0004-x86-head-Fix-head-ELF-function-annotations.patch
new/patches.suse/0004-x86-head-Fix-head-ELF-function-annotations.patch
--- old/patches.suse/0004-x86-head-Fix-head-ELF-function-annotations.patch
2017-09-12 14:57:54.000000000 +0200
+++ new/patches.suse/0004-x86-head-Fix-head-ELF-function-annotations.patch
2017-09-20 08:43:24.000000000 +0200
@@ -1,7 +1,7 @@
From: Josh Poimboeuf <jpoim...@redhat.com>
-Date: Thu, 31 Aug 2017 15:23:42 -0500
+Date: Mon, 18 Sep 2017 21:43:33 -0500
Subject: x86/head: Fix head ELF function annotations
-Patch-mainline: submitted on 8/31/2017
+Patch-mainline: submitted on 9/19/2017
References: bnc#1058115
These functions aren't callable C-type functions, so don't annotate them
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/patches.suse/0005-x86-boot-Annotate-verify_cpu-as-a-callable-function.patch
new/patches.suse/0005-x86-boot-Annotate-verify_cpu-as-a-callable-function.patch
---
old/patches.suse/0005-x86-boot-Annotate-verify_cpu-as-a-callable-function.patch
2017-09-12 14:57:54.000000000 +0200
+++
new/patches.suse/0005-x86-boot-Annotate-verify_cpu-as-a-callable-function.patch
2017-09-20 08:43:24.000000000 +0200
@@ -1,7 +1,7 @@
From: Josh Poimboeuf <jpoim...@redhat.com>
-Date: Thu, 31 Aug 2017 15:23:43 -0500
+Date: Mon, 18 Sep 2017 21:43:34 -0500
Subject: x86/boot: Annotate verify_cpu() as a callable function
-Patch-mainline: submitted on 8/31/2017
+Patch-mainline: submitted on 9/19/2017
References: bnc#1058115
verify_cpu() is a callable function. Annotate it as such.
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/patches.suse/0006-x86-xen-Fix-xen-head-ELF-annotations.patch
new/patches.suse/0006-x86-xen-Fix-xen-head-ELF-annotations.patch
--- old/patches.suse/0006-x86-xen-Fix-xen-head-ELF-annotations.patch
2017-09-12 14:57:54.000000000 +0200
+++ new/patches.suse/0006-x86-xen-Fix-xen-head-ELF-annotations.patch
2017-09-20 08:43:24.000000000 +0200
@@ -1,7 +1,7 @@
From: Josh Poimboeuf <jpoim...@redhat.com>
-Date: Thu, 31 Aug 2017 15:23:44 -0500
+Date: Mon, 18 Sep 2017 21:43:35 -0500
Subject: x86/xen: Fix xen head ELF annotations
-Patch-mainline: submitted on 8/31/2017
+Patch-mainline: submitted on 9/19/2017
References: bnc#1058115
Mark the ends of the startup_xen and hypercall_page code sections.
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/patches.suse/0007-x86-xen-Add-unwind-hint-annotations-fix.patch
new/patches.suse/0007-x86-xen-Add-unwind-hint-annotations-fix.patch
--- old/patches.suse/0007-x86-xen-Add-unwind-hint-annotations-fix.patch
2017-09-12 14:57:54.000000000 +0200
+++ new/patches.suse/0007-x86-xen-Add-unwind-hint-annotations-fix.patch
1970-01-01 01:00:00.000000000 +0100
@@ -1,28 +0,0 @@
-Subject: fix annotations of xen-head.S
-From: Jiri Slaby <jsl...@suse.cz>
-Patch-mainline: submitted on 12/9/2017
-References: bnc#1058115
-
-On i386, arch/x86/kernel/head_32.S includes xen-head.S too. Since it is
-annotated now, the assembler refuses to compile the file:
-arch/x86/kernel/../../x86/xen/xen-head.S:47: Error: no such instruction:
`unwind_hint_empty'
-scripts/Makefile.build:413: recipe for target 'arch/x86/kernel/head_32.o'
failed
-
-Include ../entry/calling.h to pull asm/unwind_hints.h where these macros are
-defined.
-
-Signed-off-by: Jiri Slaby <jsl...@suse.cz>
----
- arch/x86/kernel/head_32.S | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/x86/kernel/head_32.S
-+++ b/arch/x86/kernel/head_32.S
-@@ -25,6 +25,7 @@
- #include <asm/bootparam.h>
- #include <asm/export.h>
- #include <asm/pgtable_32.h>
-+#include "../entry/calling.h"
-
- /* Physical address */
- #define pa(X) ((X) - __PAGE_OFFSET)
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/patches.suse/0007-x86-xen-Add-unwind-hint-annotations.patch
new/patches.suse/0007-x86-xen-Add-unwind-hint-annotations.patch
--- old/patches.suse/0007-x86-xen-Add-unwind-hint-annotations.patch
2017-09-12 14:57:54.000000000 +0200
+++ new/patches.suse/0007-x86-xen-Add-unwind-hint-annotations.patch
2017-09-20 08:43:24.000000000 +0200
@@ -1,7 +1,7 @@
From: Josh Poimboeuf <jpoim...@redhat.com>
-Date: Thu, 31 Aug 2017 15:23:45 -0500
+Date: Mon, 18 Sep 2017 21:43:36 -0500
Subject: x86/xen: Add unwind hint annotations
-Patch-mainline: submitted on 8/31/2017
+Patch-mainline: submitted on 9/19/2017
References: bnc#1058115
Add unwind hint annotations to the xen head code so the ORC unwinder can
@@ -13,12 +13,20 @@
Signed-off-by: Josh Poimboeuf <jpoim...@redhat.com>
Signed-off-by: Jiri Slaby <jsl...@suse.cz>
---
- arch/x86/xen/xen-head.S | 6 +++++-
- 1 file changed, 5 insertions(+), 1 deletion(-)
+ arch/x86/xen/xen-head.S | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
--- a/arch/x86/xen/xen-head.S
+++ b/arch/x86/xen/xen-head.S
-@@ -19,6 +19,7 @@
+@@ -9,6 +9,7 @@
+ #include <asm/boot.h>
+ #include <asm/asm.h>
+ #include <asm/page_types.h>
++#include <asm/unwind_hints.h>
+
+ #include <xen/interface/elfnote.h>
+ #include <xen/interface/features.h>
+@@ -19,6 +20,7 @@
#ifdef CONFIG_XEN_PV
__INIT
ENTRY(startup_xen)
@@ -26,7 +34,7 @@
cld
/* Clear .bss */
-@@ -40,7 +41,10 @@ END(startup_xen)
+@@ -40,7 +42,10 @@ END(startup_xen)
.pushsection .text
.balign PAGE_SIZE
ENTRY(hypercall_page)
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/patches.suse/0008-x86-head-Add-unwind-hint-annotations.patch
new/patches.suse/0008-x86-head-Add-unwind-hint-annotations.patch
--- old/patches.suse/0008-x86-head-Add-unwind-hint-annotations.patch
2017-09-12 14:57:54.000000000 +0200
+++ new/patches.suse/0008-x86-head-Add-unwind-hint-annotations.patch
2017-09-20 08:43:24.000000000 +0200
@@ -1,7 +1,7 @@
From: Josh Poimboeuf <jpoim...@redhat.com>
-Date: Thu, 31 Aug 2017 15:23:46 -0500
+Date: Mon, 18 Sep 2017 21:43:37 -0500
Subject: x86/head: Add unwind hint annotations
-Patch-mainline: submitted on 8/31/2017
+Patch-mainline: submitted on 9/19/2017
References: bnc#1058115
Jiri Slaby reported an ORC issue when unwinding from an idle task. The
++++++ series.conf ++++++
--- /var/tmp/diff_new_pack.cuPo9w/_old 2017-09-23 21:32:40.619398014 +0200
+++ /var/tmp/diff_new_pack.cuPo9w/_new 2017-09-23 21:32:40.619398014 +0200
@@ -29,6 +29,7 @@
########################################################
patches.kernel.org/patch-4.13.1
patches.kernel.org/patch-4.13.1-2
+ patches.kernel.org/patch-4.13.2-3
########################################################
# Build fixes that apply to the vanilla kernel too.
@@ -314,7 +315,7 @@
########################################################
# DRM/Video
########################################################
-+jdelvare
patches.fixes/drm-amdgpu-revert-update-tile-table-for-oland-hainan.patch
+ patches.fixes/drm-amdgpu-revert-update-tile-table-for-oland.patch
########################################################
# video4linux
@@ -467,7 +468,6 @@
patches.suse/0005-x86-boot-Annotate-verify_cpu-as-a-callable-function.patch
patches.suse/0006-x86-xen-Fix-xen-head-ELF-annotations.patch
patches.suse/0007-x86-xen-Add-unwind-hint-annotations.patch
- patches.suse/0007-x86-xen-Add-unwind-hint-annotations-fix.patch
patches.suse/0008-x86-head-Add-unwind-hint-annotations.patch
# to be thrown away, I suppose
++++++ source-timestamp ++++++
--- /var/tmp/diff_new_pack.cuPo9w/_old 2017-09-23 21:32:40.659392387 +0200
+++ /var/tmp/diff_new_pack.cuPo9w/_new 2017-09-23 21:32:40.663391824 +0200
@@ -1,3 +1,3 @@
-2017-09-14 20:42:01 +0200
-GIT Revision: 68f4aeee6ce13c7bad6891759df622444734a9f1
+2017-09-20 08:43:24 +0200
+GIT Revision: 76ecbd30d4a964b37dd849e69ef3812630f8b1c9
GIT Branch: stable
