Hello community, here is the log from the commit of package cpuid for openSUSE:Factory checked in at 2018-04-20 17:32:00 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/cpuid (Old) and /work/SRC/openSUSE:Factory/.cpuid.new (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "cpuid" Fri Apr 20 17:32:00 2018 rev:6 rq:599182 version:20180419 Changes: -------- --- /work/SRC/openSUSE:Factory/cpuid/cpuid.changes 2017-01-24 10:40:38.260752343 +0100 +++ /work/SRC/openSUSE:Factory/.cpuid.new/cpuid.changes 2018-04-20 17:34:04.552517434 +0200 @@ -1,0 +2,13 @@ +Fri Apr 20 06:33:28 UTC 2018 - [email protected] + +- Update to new upstream release 20180419 + * Added synth decoding for AMD Zen, Pentium Silver (Gemini + Lake), Xeon Scalable (Bronze, Silver, Gold, Platinium) + (Skylake), Core X-Series (Skylake-X), Bay Trail D0, Bay Trail + A0, Xeon E7-4800/8800 (Broadwell-EX B0), Xeon D-1500N + (Broadwell-DE A1), Bay Trail-I (E3800), Avoton C0 stepping. + * Corrected synth decoding for Bay Trail-M C0 steppings. + * Added new Intel 1b leaf from Intel Architecture. + * Added various bit fields. + +------------------------------------------------------------------- Old: ---- cpuid-20170122.src.tar.gz New: ---- cpuid-20180419.src.tar.gz ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ cpuid.spec ++++++ --- /var/tmp/diff_new_pack.cKopWO/_old 2018-04-20 17:34:05.220493209 +0200 +++ /var/tmp/diff_new_pack.cKopWO/_new 2018-04-20 17:34:05.224493065 +0200 @@ -1,7 +1,7 @@ # # spec file for package cpuid # -# Copyright (c) 2017 SUSE LINUX GmbH, Nuernberg, Germany. +# Copyright (c) 2018 SUSE LINUX GmbH, Nuernberg, Germany. # # All modifications and additions to the file contributed by third parties # remain the property of their copyright owners, unless otherwise agreed @@ -17,10 +17,10 @@ Name: cpuid -Version: 20170122 +Version: 20180419 Release: 0 Summary: x86 CPU identification tool -License: GPL-2.0+ +License: GPL-2.0-or-later Group: System/Management Url: http://etallen.com/cpuid.html ++++++ cpuid-20170122.src.tar.gz -> cpuid-20180419.src.tar.gz ++++++ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20170122/ChangeLog new/cpuid-20180419/ChangeLog --- old/cpuid-20170122/ChangeLog 2017-01-22 21:51:24.000000000 +0100 +++ new/cpuid-20180419/ChangeLog 2018-04-19 16:19:06.000000000 +0200 @@ -1,3 +1,67 @@ +Thu Apr 19 2018 Todd Allen <[email protected]> + * Made new release. + +Wed Apr 19 2018 Todd Allen <[email protected]> + * cpuid.c: Fixed various bugs reported by Stefan Kanthak: + * cpuid.c: Fixed bug in print_2_meaning: 0x49 normal & special cases. + * cpuid.c: Fixed bug in print_2_meaning: 0x63 additional 2M/4M, 4-way, + 32 entries item. + * cpuid.c: Collapsed print_2_meaning into print_2_byte so that the + prefix and CONT are known in one place. + * cpuid.c: Fixed bug in print_2_byte: 0x7d is not sectored. + * cpuid.c: Fixed bug in print_2_byte: 0xc2 is 4K, not 4M. + * cpuid.c: Changed 6/ecx bit 0 to "hardware coordination feedback". + * cpuid.c; Changed 7/ebx bit 3 to "BMI1 instructions". + * cpuid.c: Change 7/ebx bit 12 to RDT-M. + * cpuid.c: Change 7/ebx bit 15 to RDT-A. + * cpuid.c: Corrected "0x40000003/ecx" label. + * cpuid.c; print_40000003_edx_microsoft: corrected "idle" spelling. + +Wed Apr 19 2018 Todd Allen <[email protected]> + * cpuid.c: Added mnemonic letters for some 1/ecx, 1/edx, and 7/ebx leaf + fields. + * cpuid.c: Fixed bug with 4/ecx: field name should be "number of sets". + * cpuid.c: Fixed bug with 4/ecx leaf: pass ECX to it! + * cpuid.c; Fixed bug with 0x10/ecx: pass ECX to it! + * cpuid.c: Fixed bug with 0x10/edx: pass EDX to it! + +Sun Apr 8 2018 Todd Allen <[email protected]> + * cpuid.c: Added 2 leaf 0xfe encoding: TLB data in leaf 0x18. + * cpuid.c: Added new Intel 6/eax bit fields. + * cpuid.c: Added new Intel a/edx bit field: anythread deprecation. + * cpuid.c: Added new Intel d/0/eax bit field: IA32_XSS HDC state. + * cpuid.c: Added new Intel 10/0/ebx bit field: memory bandwidth alloc. + * cpuid.c: Added new Intel 12/0/eax bit fields + * cpuid.c: Added new Intel 18 leaf: deterministic address translation. + * cpuid.c: Added new Intel 7/ecx bit fields from Intel Architecture + Instruction Set Extensions and Future Features Programming Reference. + * cpuid.c: Added new Intel 1b leaf from Intel Architecture + Instruction Set Extensions and Future Features Programming Reference. + * cpuid.c: Added synth decoding for Avoton C0 stepping (same as B0). + * cpuid.c: Corrected synth decoding for Bay Trail-M C0 steppings. + * cpuid.c: Added synth decoding for Bay Trail-I (E3800). + * cpuid.c: Added synth decoding for Xeon D-1500N (Broadwell-DE A1). + * cpuid.c: Added synth decoding for Xeon E7-4800/8800 (Broadwell-EX B0). + * cpuid.c: Correct synth decoding for Bay Trail A0. + * cpuid.c: Added synth decoding for Bay Trail D0. + * cpuid.c: Added synth decoding for Core X-Series (Skylake-X). + * cpuid.c: Added synth decoding for Xeon Scalable (Bronze, Silver, Gold, + Platinium) (Skylake). + * cpuid.c: Added synth decoding for Pentium Silver (Gemini Lake). + * cpuid.c: Added synth decoding for AMD Zen. + * cpuid.man: Added new spec updates & PPR. + +Fri Nov 3 2017 Todd Allen <[email protected]> + * cpuid.c, cpuid.man: Attribute whitepaper to Shih Kuo. + +Wed Jun 22 2017 Lars Wendler <[email protected]> + * cpuid.c: recent glibc versions no longer automagically include + sysmacros.h headers. This needs to be done by the source files itself + now. + +Fri Mar 3 2017 Todd Allen <[email protected]> + * cpuid.c: Added missing SDBG bit to 1/ecx leaf. + Sun Jan 22 2017 Todd Allen <[email protected]> * Made new release. * cpuid.c: Use __cpuid_count macro for "cpuid" instruction if possible. @@ -20,8 +84,8 @@ it seems likely other people do too. * cpuid.c: Added synth decoding for Quark X1000. * cpuid.c: Added Intel Atom Z2760 (Clover Trail). - * cpuid.c; Added extra synth decodings for some Sandy Bridge processors. - * cpuid.c; Added extra synth decodings for some Ivy Bridge processors. + * cpuid.c: Added extra synth decodings for some Sandy Bridge processors. + * cpuid.c: Added extra synth decodings for some Ivy Bridge processors. * cpuid.man: Added new & missing spec updates & revision guides. * FUTURE: Cleaned this up somewhat. diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20170122/Makefile new/cpuid-20180419/Makefile --- old/cpuid-20170122/Makefile 2017-01-22 18:07:21.000000000 +0100 +++ new/cpuid-20180419/Makefile 2018-04-19 16:19:28.000000000 +0200 @@ -7,7 +7,7 @@ CFL=$(CPPFLAGS) $(CFLAGS) $(CISA) -Wall -Wshadow -Wcast-align -Wredundant-decls -Wbad-function-cast -Wcast-qual -Wwrite-strings -Waggregate-return -Wstrict-prototypes -Wmissing-prototypes -D_FILE_OFFSET_BITS=64 -DVERSION=$(VERSION) PACKAGE=cpuid -VERSION=20170122 +VERSION=20180419 RELEASE=1 PROG=$(PACKAGE) diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20170122/cpuid.c new/cpuid-20180419/cpuid.c --- old/cpuid-20170122/cpuid.c 2017-01-22 21:51:17.000000000 +0100 +++ new/cpuid-20180419/cpuid.c 2018-04-19 16:15:07.000000000 +0200 @@ -1,6 +1,6 @@ /* ** cpuid dumps CPUID information for each CPU. -** Copyright 2003,2004,2005,2006,2010,2011,2012,2013,2014,2015,2016,2017 by +** Copyright 2003,2004,2005,2006,2010,2011,2012,2013,2014,2015,2016,2017,2018 by ** Todd Allen. ** ** This program is free software; you can redistribute it and/or @@ -31,6 +31,7 @@ #include <stdio.h> #include <sys/types.h> #include <sys/stat.h> +#include <sys/sysmacros.h> #include <fcntl.h> #include <errno.h> #include <unistd.h> @@ -1415,7 +1416,8 @@ stash->br.core = strstr(brand, "Core(TM)") != NULL; stash->br.pentium = strstr(brand, "Pentium") != NULL; stash->br.xeon_mp = (strstr(brand, "Xeon MP") != NULL - || strstr(brand, "Xeon(TM) MP") != NULL); + || strstr(brand, "Xeon(TM) MP") != NULL + || strstr(brand, "Xeon(R)") != NULL); stash->br.xeon = strstr(brand, "Xeon") != NULL; stash->br.pentium_m = strstr(brand, "Pentium(R) M") != NULL; stash->br.pentium_d = strstr(brand, "Pentium(R) D") != NULL; @@ -2145,13 +2147,14 @@ // from [email protected] does. FMS ( 0, 6, 3, 6, 1, "Intel Atom D2000/N2000 (Cedarview B1/B2/B3) / S1200 (Centerton B1), 32nm"); FM ( 0, 6, 3, 6, "Intel Atom D2000/N2000 (Cedarview) / S1200 (Centerton B1), 32nm"); - FMS ( 0, 6, 3, 7, 1, "Intel Atom Z3000 (Bay Trail-T B2/B3), 22nm"); - FMS ( 0, 6, 3, 7, 2, "Intel Pentium / Celeron (Bay Trail-M B1), 22nm"); - FMS ( 0, 6, 3, 7, 3, "Intel Pentium N3500 / J2850 / Celeron N1700 / N1800 / N2800 / N2900 (Bay Trail-M B2/B3), 22nm"); - FMSQ( 0, 6, 3, 7, 8, dC, "Intel Celeron N2800 / N2900 (Bay Trail-M C0), 22nm"); - FMSQ( 0, 6, 3, 7, 8, dP, "Intel Pentium N3500 (Bay Trail-M C0), 22nm"); - FMS ( 0, 6, 3, 7, 8, "Intel Pentium N3500 / Celeron N2800 / N2900 (Bay Trail-M C0) / Atom Z3000 (Bay Trail-T B2/B3), 22nm"); - FM ( 0, 6, 3, 7, "Intel Pentium N3500 / J2850 / Celeron N1700 / N1800 / N2800 / N2900 (Bay Trail-M) / Atom Z3000 (Bay Trail-T), 22nm"); + FMS ( 0, 6, 3, 7, 1, "Intel Atom Z3000 (Bay Trail-T A0), 22nm"); + FMS ( 0, 6, 3, 7, 2, "Intel Pentium / Celeron (Bay Trail-M B0/B1), 22nm"); + FMS ( 0, 6, 3, 7, 3, "Intel Pentium N3500 / J2850 / Celeron N1700 / N1800 / N2800 / N2900 (Bay Trail-M B2/B3) / Atom E3800 (Bay Trail-I B3), 22nm"); + FMSQ( 0, 6, 3, 7, 4, dC, "Intel Celeron N2800 / N2900 (Bay Trail-M C0), 22nm"); + FMSQ( 0, 6, 3, 7, 4, dP, "Intel Pentium N3500 (Bay Trail-M C0), 22nm"); + FMS ( 0, 6, 3, 7, 4, "Intel Pentium N3500 / Celeron N2800 / N2900 (Bay Trail-M C0) / Atom Z3000 (Bay Trail-T B2/B3), 22nm"); + FMS ( 0, 6, 3, 7, 9, "Intel Atom E3800 (Bay Trail-I D0), 22nm"); + FM ( 0, 6, 3, 7, "Intel Pentium N3500 / J2850 / Celeron N1700 / N1800 / N2800 / N2900 (Bay Trail-M) / Atom Z3000 (Bay Trail-T) / Atom E3800 (Bay Trail-I), 22nm"); FMSQ( 0, 6, 3,10, 9, Mc, "Intel Mobile Core i3-3000 (Ivy Bridge L1) / i5-3000 (Ivy Bridge L1) / i7-3000 (Ivy Bridge E1/L1) / Pentium 900/1000/2000/2100 (P0), 22nm"); FMSQ( 0, 6, 3,10, 9, dc, "Intel Core i3-3000 (Ivy Bridge L1) / i5-3000 (Ivy Bridge E1/N0/L1) / i7-3000 (Ivy Bridge E1), 22nm"); FMSQ( 0, 6, 3,10, 9, sX, "Intel Xeon E3-1100 v2 / E3-1200 v2 (Ivy Bridge E1/N0/L1), 22nm"); @@ -2212,7 +2215,7 @@ FMS ( 0, 6, 4,12, 0, "Intel Pentium N3000 / Celeron N3000 (Braswell C0), 14nm"); FM ( 0, 6, 4,12, "Intel Pentium N3000 / Celeron N3000 (Braswell), 14nm"); FMS ( 0, 6, 4,13, 0, "Intel Atom C2000 (Avoton A0/A1), 22nm"); - FMS ( 0, 6, 4,13, 8, "Intel Atom C2000 (Avoton B0), 22nm"); + FMS ( 0, 6, 4,13, 8, "Intel Atom C2000 (Avoton B0/C0), 22nm"); FM ( 0, 6, 4,13, "Intel Atom C2000 (Avoton), 22nm"); // Intel docs (332689) omit the stepping numbers for (0,6),(4,14) D1 & K1. FMQ ( 0, 6, 4,14, dc, "Intel Core i3-6000U / i5-6000U / i7-6000U / m3-6Y00 / m5-6Y00 / m7-6Y00 (Skylake), 14nm"); @@ -2223,13 +2226,22 @@ // Intel docs (334208,333811) omit the stepping numbers for (0,6),(4,15) // B0, M0 & R0. FMQ ( 0, 6, 4,15, dc, "Intel Core i7-6800K / i7-6900K / i7-6900X (Broadwell-E), 14nm"); + FMSQ( 0, 6, 4,15, 1, sX, "Intel Xeon E5-1600 / E5-2600 / E5-4600 v4 (Broadwell) / E7-4800 / E7-8800 v4 (Broadwell-EX B0), 14nm"); FMQ ( 0, 6, 4,15, sX, "Intel Xeon E5-1600 / E5-2600 / E5-4600 v4 (Broadwell) / E7-4800 / E7-8800 v4 (Broadwell-EX), 14nm"); FM ( 0, 6, 4,15, "Intel Core i7-6800K / i7-6900K / i7-6900X (Broadwell-E) / Xeon E5-1600 / E5-2500 / E5-4600 (Broadwell) / E7-4800 / E7-8800 v4 (Broadwell-EX), 14nm"); + FMSQ( 0, 6, 5, 5, 2, sX, "Intel Xeon W 2000 / Scalable Bronze 3000 / Silver 4000 / Gold 5000 / 6000 / Platinum 8000 (Skylake B0/L0), 14nm"); + FMSQ( 0, 6, 5, 5, 4, sX, "Intel Xeon W 2000 / Scalable Bronze 3000 / Silver 4000 / Gold 5000 / 6000 / Platinum 8000 (Skylake H0/M0/U0), 14nm"); + // Intel docs (335901) omit almost all details for the Core versions of + // (0,6),(5,5). + FMQ ( 0, 6, 5, 5, dc, "Intel Core i7-6000X / i7-7000X / i9-7000X (Skylake-X), 14nm"); + FMQ ( 0, 6, 5, 5, sX, "Intel Xeon W 2000 / Scalable Bronze 3000 / Silver 4000 / Gold 5000 / 6000 / Platinum 8000 (Skylake), 14nm"); + FM ( 0, 6, 5, 5, "Intel Core i7-6000X / i7-7000X / i9-7000X (Skylake-X) / Xeon W 2000 / Scalable Bronze 3000 / Silver 4000 / Gold 5000 / 6000 / Platinum 8000 (Skylake), 14nm"); FMS ( 0, 6, 5, 6, 1, "Intel Xeon D-1500 (Broadwell-DE U0), 14nm"); FMS ( 0, 6, 5, 6, 2, "Intel Xeon D-1500 (Broadwell-DE V1), 14nm"); FMS ( 0, 6, 5, 6, 3, "Intel Xeon D-1500 (Broadwell-DE V2), 14nm"); FMS ( 0, 6, 5, 6, 4, "Intel Xeon D-1500 (Broadwell-DE Y0), 14nm"); - FM ( 0, 6, 5, 6, "Intel Xeon D-1500 (Broadwell-DE), 14nm"); + FMS ( 0, 6, 5, 6, 5, "Intel Xeon D-1500N (Broadwell-DE A1), 14nm"); + FM ( 0, 6, 5, 6, "Intel Xeon D-1500 / D-1500N (Broadwell-DE), 14nm"); // Intel docs (334646) omit the stepping number for B0. But as of Jan 2017, // it is the only stepping, and all examples seen have stepping number 1. FMS ( 0, 6, 5, 7, 1, "Intel Xeon Phi x200 (Knights Landing B0), 14nm"); @@ -2249,15 +2261,20 @@ FMQ ( 0, 6, 5,14, sX, "Intel Xeon E3-1200 v5 (Skylake), 14nm"); FM ( 0, 6, 5,14, "Intel Core i3-6000 / i5-6000 / i7-6000 / Pentium G4000 / Celeron G3900 / Xeon E3-1200 (Skylake), 14nm"); FM ( 0, 6, 5,15, "Intel Atom (Goldmont), 14nm"); // no spec update; only 325462 Volume 3 Table 35-1 so far + FMS ( 0, 6, 7,10, 1, "Intel Pentium Silver N5000 / J5000 / Celeron N4000 / J4000 (Gemini Lake B0), 14nm"); + FM ( 0, 6, 7,10, "Intel Pentium Silver N5000 / J5000 / Celeron N4000 / J4000 (Gemini Lake), 14nm"); FM ( 0, 6, 8, 5, "Intel Xeon Phi (Knights Mill), 14nm"); // no spec update; 325462 Volume 3 Table 35-1 is vague; Piotr Luc said it would be Knights Mill - // So far, all these (0,6),(8,14) processors are stepping H0, but the - // Intel docs (334663) omit the stepping number for H0. + // Intel docs (334663) omit the stepping numbers for (0,6),(8,14) + // H0, J1 & Y0. FMQ ( 0, 6, 8,14, dc, "Intel m3-7Y00 / i5-7Y00 / i7-7Y00 / i3-7000U / i5-7000U / i7-7000U (Kaby Lake), 14nm"); FMQ ( 0, 6, 8,14, dP, "Intel Pentium 4410Y / 4415U (Kaby Lake), 14nm"); FMQ ( 0, 6, 8,14, dC, "Intel Celeron 3965Y / 3865U / 3965U (Kaby Lake), 14nm"); FM ( 0, 6, 8,14, "Intel m3-7Y00 / i5-7Y00 / i7-7Y00 / i3-7000U / i5-7000U / i7-7000U / Pentium 4410Y / 4415U / Celeron 3965Y / 3865U / 3965U (Kaby Lake), 14nm"); - FMQ ( 0, 6, 9,14, dc, "Intel Core i5-7000 / i5-7000K / i5-7000T / i7-7000 / E3-15x5MV6 / i3-7100H / i5-7000HQ / i7-7000HQ (Kaby Lake), 14nm"); - FM ( 0, 6, 9,14, "Intel Core i5-7000 / i5-7000K / i5-7000T / i7-7000 / E3-15x5MV6 / i3-7100H / i5-7000HQ / i7-7000HQ (Kaby Lake), 14nm"); + // Intel docs (334663) omit the stepping numbers for (0,6),(9,14) B0. + FMQ ( 0, 6, 9,14, dc, "Intel Core i5-7000 / i5-7000K / i5-7000T / i7-7000 / i3-7100H / i5-7000HQ / i7-7000HQ / i7-7000X / i5-7000X / i7-8000 / i5-8000 / i3-8000 (Kaby Lake), 14nm"); + FMQ ( 0, 6, 9,14, dC, "Intel Celeron G3930 (Kaby Lake), 14nm"); + FMQ ( 0, 6, 9,14, sX, "Intel Xeon E3-1200v6 / E3-1285v5 / E3-15x5Mv6 (Kaby Lake), 14nm"); + FM ( 0, 6, 9,14, "Intel Core i5-7000 / i5-7000K / i5-7000T / i7-7000 / i3-7100H / i5-7000HQ / i7-7000HQ / i7-7000X / i5-7000X / i7-8000 / i5-8000 / i3-8000 / Xeon E3-1200v6 / E3-1285v5 / E3-15x5Mv6 / Celeron G3930 (Kaby Lake), 14nm"); FQ ( 0, 6, sX, "Intel Xeon (unknown model)"); FQ ( 0, 6, se, "Intel Xeon (unknown model)"); FQ ( 0, 6, MC, "Intel Mobile Celeron (unknown model)"); @@ -2982,6 +2999,8 @@ // recent AMD pattern, these must be (7,15),(3,0). FMS (7,15, 3, 0, 1, "AMD A-Series / E-Series Series (Mullins ML-A1) [Puma 2014], 28nm"); FM (7,15, 3, 0, "AMD A-Series / E-Series Series (Mullins) [Puma 2014], 28nm"); + FMS (8,15, 0, 1, 1, "AMD Ryzen (Summit Ridge B1) [Zen], 14nm"); + FM (8,15, 0, 1, "AMD Ryzen (Summit Ridge) [Zen], 14nm"); DEFAULT ("unknown"); const char* brand_pre; @@ -3349,6 +3368,7 @@ ** by Khang Nguyen and Shihjong Kuo ** and: ** Intel 64 Architecture Processor Topology Enumeration (Whitepaper) + ** by Shih Kuo */ if (stash->saw_b) { unsigned int ht = GET_X2APIC_PROCESSORS(stash->val_b_ebx[0]); @@ -3503,6 +3523,7 @@ ** by Khang Nguyen and Shihjong Kuo ** and: ** Intel 64 Architecture Processor Topology Enumeration (Whitepaper) + ** by Shih Kuo */ if (stash->saw_b) { smt_width = GET_X2APIC_WIDTH(stash->val_b_eax[0]); @@ -3731,24 +3752,25 @@ static named_item names[] = { { "PNI/SSE3: Prescott New Instructions" , 0, 0, bools }, { "PCLMULDQ instruction" , 1, 1, bools }, - { "64-bit debug store" , 2, 2, bools }, + { "DTES64: 64-bit debug store" , 2, 2, bools }, { "MONITOR/MWAIT" , 3, 3, bools }, { "CPL-qualified debug store" , 4, 4, bools }, { "VMX: virtual machine extensions" , 5, 5, bools }, { "SMX: safer mode extensions" , 6, 6, bools }, { "Enhanced Intel SpeedStep Technology" , 7, 7, bools }, - { "thermal monitor 2" , 8, 8, bools }, + { "TM2: thermal monitor 2" , 8, 8, bools }, { "SSSE3 extensions" , 9, 9, bools }, { "context ID: adaptive or shared L1 data" , 10, 10, bools }, + { "SDBG: IA32_DEBUG_INTERFACE" , 11, 11, bools }, { "FMA instruction" , 12, 12, bools }, { "CMPXCHG16B instruction" , 13, 13, bools }, { "xTPR disable" , 14, 14, bools }, - { "perfmon and debug" , 15, 15, bools }, - { "process context identifiers" , 17, 17, bools }, - { "direct cache access" , 18, 18, bools }, + { "PDCM: perfmon and debug" , 15, 15, bools }, + { "PCID: process context identifiers" , 17, 17, bools }, + { "DCA: direct cache access" , 18, 18, bools }, { "SSE4.1 extensions" , 19, 19, bools }, { "SSE4.2 extensions" , 20, 20, bools }, - { "extended xAPIC support" , 21, 21, bools }, + { "x2APIC: extended xAPIC support" , 21, 21, bools }, { "MOVBE instruction" , 22, 22, bools }, { "POPCNT instruction" , 23, 23, bools }, { "time stamp counter deadline" , 24, 24, bools }, @@ -3771,35 +3793,35 @@ { static named_item names[] = { { "x87 FPU on chip" , 0, 0, bools }, - { "virtual-8086 mode enhancement" , 1, 1, bools }, - { "debugging extensions" , 2, 2, bools }, - { "page size extensions" , 3, 3, bools }, - { "time stamp counter" , 4, 4, bools }, + { "VME: virtual-8086 mode enhancement" , 1, 1, bools }, + { "DE: debugging extensions" , 2, 2, bools }, + { "PSE: page size extensions" , 3, 3, bools }, + { "TSC: time stamp counter" , 4, 4, bools }, { "RDMSR and WRMSR support" , 5, 5, bools }, - { "physical address extensions" , 6, 6, bools }, - { "machine check exception" , 7, 7, bools }, + { "PAE: physical address extensions" , 6, 6, bools }, + { "MCE: machine check exception" , 7, 7, bools }, { "CMPXCHG8B inst." , 8, 8, bools }, { "APIC on chip" , 9, 9, bools }, { "SYSENTER and SYSEXIT" , 11, 11, bools }, - { "memory type range registers" , 12, 12, bools }, + { "MTRR: memory type range registers" , 12, 12, bools }, { "PTE global bit" , 13, 13, bools }, - { "machine check architecture" , 14, 14, bools }, - { "conditional move/compare instruction" , 15, 15, bools }, - { "page attribute table" , 16, 16, bools }, - { "page size extension" , 17, 17, bools }, - { "processor serial number" , 18, 18, bools }, + { "MCA: machine check architecture" , 14, 14, bools }, + { "CMOV: conditional move/compare instr" , 15, 15, bools }, + { "PAT: page attribute table" , 16, 16, bools }, + { "PSE-36: page size extension" , 17, 17, bools }, + { "PSN: processor serial number" , 18, 18, bools }, { "CLFLUSH instruction" , 19, 19, bools }, - { "debug store" , 21, 21, bools }, - { "thermal monitor and clock ctrl" , 22, 22, bools }, + { "DS: debug store" , 21, 21, bools }, + { "ACPI: thermal monitor and clock ctrl" , 22, 22, bools }, { "MMX Technology" , 23, 23, bools }, { "FXSAVE/FXRSTOR" , 24, 24, bools }, { "SSE extensions" , 25, 25, bools }, { "SSE2 extensions" , 26, 26, bools }, - { "self snoop" , 27, 27, bools }, + { "SS: self snoop" , 27, 27, bools }, { "hyper-threading / multi-core supported" , 28, 28, bools }, - { "therm. monitor" , 29, 29, bools }, + { "TM: therm. monitor" , 29, 29, bools }, { "IA64" , 30, 30, bools }, - { "pending break event" , 31, 31, bools }, + { "PBE: pending break event" , 31, 31, bools }, }; printf(" feature information (1/edx):\n"); @@ -3807,10 +3829,15 @@ /* max_len => */ 0); } -static void print_2_meaning(unsigned char value, - vendor_t vendor, - unsigned int val_1_eax) +static void print_2_byte(unsigned char value, + vendor_t vendor, + unsigned int val_1_eax) { + if (value == 0x00) return; + + printf(" 0x%02x: ", value); +#define CONT "\n " + if (vendor == VENDOR_CYRIX || vendor == VENDOR_VIA) { switch (value) { case 0x70: printf("TLB: 4K pages, 4-way, 32 entries"); return; @@ -3868,7 +3895,12 @@ case 0x46: printf("L3 cache: 4M, 4-way, 64 byte lines"); break; case 0x47: printf("L3 cache: 8M, 8-way, 64 byte lines"); break; case 0x48: printf("L2 cache: 3M, 12-way, 64 byte lines"); break; - case 0x49: printf("L3 cache: 4M, 16-way, 64 byte lines"); break; + case 0x49: if (__FM(val_1_eax) == _XF(0) + _F(15) + _XM(0) + _M(6)) { + printf("L3 cache: 4M, 16-way, 64 byte lines"); + } else { + printf("L2 cache: 4M, 16-way, 64 byte lines"); + } + break; case 0x4a: printf("L3 cache: 6M, 12-way, 64 byte lines"); break; case 0x4b: printf("L3 cache: 8M, 16-way, 64 byte lines"); break; case 0x4c: printf("L3 cache: 12M, 12-way, 64 byte lines"); break; @@ -3888,7 +3920,8 @@ case 0x5d: printf("data TLB: 4K & 4M pages, 256 entries"); break; case 0x60: printf("L1 data cache: 16K, 8-way, 64 byte lines"); break; case 0x61: printf("instruction TLB: 4K pages, 48 entries"); break; - case 0x63: printf("data TLB: 1G pages, 4-way, 4 entries"); break; + case 0x63: printf("data TLB: 2M/4M pages, 4-way, 32 entries"); + printf(CONT "data TLB: 1G pages, 4-way, 4 entries"); break; case 0x64: printf("data TLB: 4K pages, 4-way, 512 entries"); break; case 0x66: printf("L1 data cache: 8K, 4-way, 64 byte lines"); break; case 0x67: printf("L1 data cache: 16K, 4-way, 64 byte lines"); break; @@ -3909,7 +3942,7 @@ case 0x7a: printf("L2 cache: 256K, 8-way, sectored, 64 byte lines"); break; case 0x7b: printf("L2 cache: 512K, 8-way, sectored, 64 byte lines"); break; case 0x7c: printf("L2 cache: 1M, 8-way, sectored, 64 byte lines"); break; - case 0x7d: printf("L2 cache: 2M, 8-way, sectored, 64 byte lines"); break; + case 0x7d: printf("L2 cache: 2M, 8-way, 64 byte lines"); break; case 0x7e: printf("L2 cache: 256K, 8-way, sectored, 128 byte lines"); break; case 0x7f: printf("L2 cache: 512K, 2-way, 64 byte lines"); break; case 0x80: printf("L2 cache: 512K, 8-way, 64 byte lines"); break; @@ -3938,7 +3971,7 @@ case 0xba: printf("data TLB: 4K pages, 4-way, 64 entries"); break; case 0xc0: printf("data TLB: 4K & 4M pages, 4-way, 8 entries"); break; case 0xc1: printf("L2 TLB: 4K/2M pages, 8-way, 1024 entries"); break; - case 0xc2: printf("data TLB: 2M/4M pages, 4-way, 16 entries"); break; + case 0xc2: printf("data TLB: 4K & 2M pages, 4-way, 16 entries"); break; case 0xc3: printf("L2 TLB: 4K/2M pages, 6-way, 1536 entries"); break; case 0xc4: printf("data TLB: 2M/4M pages, 4-way, 32 entries"); break; case 0xca: printf("L2 TLB: 4K pages, 4-way, 512 entries"); break; @@ -3959,7 +3992,8 @@ case 0xec: printf("L3 cache: 24M, 24-way, 64 byte lines"); break; case 0xf0: printf("64 byte prefetching"); break; case 0xf1: printf("128 byte prefetching"); break; - case 0xff: printf("cache data is in CPUID 4"); break; + case 0xfe: printf("TLB data is in CPUID leaf 0x18"); break; + case 0xff: printf("cache data is in CPUID leaf 4"); break; default: printf("unknown"); break; } @@ -3967,17 +4001,9 @@ ** WARNING: If you add values here, you probably need to update the code in ** stash_intel_cache, too. */ -} - -static void print_2_byte(unsigned char value, - vendor_t vendor, - unsigned int val_1_eax) -{ - if (value == 0x00) return; - printf(" 0x%02x: ", value); - print_2_meaning(value, vendor, val_1_eax); printf("\n"); +#undef CONT } static void @@ -4017,7 +4043,7 @@ print_4_ecx(unsigned int value) { static named_item names[] - = { { "ways of associativity" , 0, 31, NIL_IMAGES }, + = { { "number of sets - 1" , 0, 31, NIL_IMAGES }, }; print_names(value, names, LENGTH(names, named_item), @@ -4105,6 +4131,12 @@ { "HWP energy performance preference" , 10, 10, bools }, { "HWP package level request" , 11, 11, bools }, { "HDC base registers" , 13, 13, bools }, + { "Intel Turbo Boost Max Technology 3.0" , 14, 14, bools }, + { "HWP capabilities" , 15, 15, bools }, + { "HWP PECI override" , 16, 16, bools }, + { "flexible HWP" , 17, 17, bools }, + { "IA32_HWP_REQUEST MSR fast access mode" , 18, 18, bools }, + { "ignoring idle logical processor HWP req" , 20, 20, bools }, }; print_names(value, names, LENGTH(names, named_item), @@ -4126,7 +4158,7 @@ print_6_ecx(unsigned int value) { static named_item names[] - = { { "ACNT/MCNT supported performance measure" , 0, 0, bools }, + = { { "hardware coordination feedback" , 0, 0, bools }, { "ACNT2 available" , 1, 1, bools }, { "performance-energy bias capability" , 3, 3, bools }, }; @@ -4142,7 +4174,7 @@ = { { "FSGSBASE instructions" , 0, 0, bools }, { "IA32_TSC_ADJUST MSR supported" , 1, 1, bools }, { "SGX: Software Guard Extensions supported", 2, 2, bools }, - { "BMI instruction" , 3, 3, bools }, + { "BMI1 instructions" , 3, 3, bools }, { "HLE hardware lock elision" , 4, 4, bools }, { "AVX2: advanced vector extensions 2" , 5, 5, bools }, { "FDP_EXCPTN_ONLY" , 6, 6, bools }, @@ -4151,10 +4183,10 @@ { "enhanced REP MOVSB/STOSB" , 9, 9, bools }, { "INVPCID instruction" , 10, 10, bools }, { "RTM: restricted transactional memory" , 11, 11, bools }, - { "QM: quality of service monitoring" , 12, 12, bools }, + { "RDT-M: Intel RDT monitoring" , 12, 12, bools }, { "deprecated FPU CS/DS" , 13, 13, bools }, - { "intel memory protection extensions" , 14, 14, bools }, - { "PQE: platform quality of service enforce", 15, 15, bools }, + { "MPX: intel memory protection extensions" , 14, 14, bools }, + { "RDT-A: Intel RDT allocation" , 15, 15, bools }, { "AVX512F: AVX-512 foundation instructions", 16, 16, bools }, { "AVX512DQ: double & quadword instructions", 17, 17, bools }, { "RDSEED instruction" , 18, 18, bools }, @@ -4185,8 +4217,19 @@ { "UMIP: user-mode instruction prevention" , 2, 2, bools }, { "PKU protection keys for user-mode" , 3, 3, bools }, { "OSPKE CR4.PKE and RDPKRU/WRPKRU" , 4, 4, bools }, + { "WAITPKG instructions" , 5, 5, bools }, + { "AVX512_VBMI2" , 6, 6, bools }, + { "GFNI: Galois Field New Instructions" , 8, 8, bools }, + { "VAES instructions" , 9, 9, bools }, + { "VPCLMULQDQ instruction" , 10, 10, bools }, + { "AVX512_VNNI" , 11, 11, bools }, + { "AVX512_BITALG: bit count/shiffle" , 12, 12, bools }, + { "AVX512: VPOPCNTDQ instruction" , 14, 14, bools }, { "BNDLDX/BNDSTX MAWAU value in 64-bit mode", 17, 21, NIL_IMAGES }, { "RDPID: read processor D supported" , 22, 22, bools }, + { "CLDEMOTE supports cache line demote" , 25, 25, bools }, + { "MOVDIRI instruction" , 27, 27, bools }, + { "MOVDIR64B intruction" , 28, 28, bools }, { "SGX_LC: SGX launch config supported" , 30, 30, bools }, }; @@ -4200,6 +4243,8 @@ static named_item names[] = { { "AVX512_4VNNIW: neural network instrs" , 2, 2, bools }, { "AVX512_4FMAPS: multiply acc single prec" , 3, 3, bools }, + { "fast short REP MOV" , 4, 4, bools }, + { "PCONFIG" , 18, 18, bools }, }; print_names(value, names, LENGTH(names, named_item), /* max_len => */ 40); @@ -4244,6 +4289,7 @@ static named_item names[] = { { "number of fixed counters" , 0, 4, NIL_IMAGES }, { "bit width of fixed counters" , 5, 12, NIL_IMAGES }, + { "anythread deprecation" , 15, 15, bools }, }; printf(" Architecture Performance Monitoring Features (0xa/edx):\n"); @@ -4294,11 +4340,13 @@ /* ** State component bitmaps in general are described in 325462: Intel 64 and ** IA-32 Architectures Software Developer's Manual Combined Volumes: 1, 2A, - ** 2B, 2C, 3A, 3B, and 3C, section 13.1: XSAVE-Supported Features and - ** State-Component Bitmaps. This leaf describes which of the bits are - ** actually supported by the hardware, and is described better in 1.32: - ** Enumeration of CPU Support for XSAVE Instructions and XSAVE-Supported - ** Features. + ** 2B, 2C, 3A, 3B, and 3C, Volume 1: Basic Architecture, section 13.1: + ** XSAVE-Supported Features and State-Component Bitmaps. This leaf describes + ** which of the bits are actually supported by the hardware, and is described + ** better in 13.2: Enumeration of CPU Support for XSAVE Instructions and + ** XSAVE-Supported Features. + ** + ** These align with the supported features[] in print_d_n() for values > 1. */ static named_item names[] = { { " XCR0 supported: x87 state" , 0, 0, bools }, @@ -4311,6 +4359,7 @@ { " XCR0 supported: AVX-512 Hi16_ZMM" , 7, 7, bools }, { " IA32_XSS supported: PT state" , 8, 8, bools }, { " XCR0 supported: PKRU state" , 9, 9, bools }, + { " IA32_XSS supported: HDC state" , 13, 13, bools }, }; print_names(value, names, LENGTH(names, named_item), @@ -4353,7 +4402,9 @@ /* ** The XSAVE areas are explained in 325462: Intel 64 and IA-32 Architectures ** Software Developer's Manual Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B, and - ** 3C, section 13.1: XSAVE-Supported Features and State-Component Bitmaps. + ** 3C, Volume 1: Basic Architecture, section 13.1: XSAVE-Supported Features + ** and State-Component Bitmaps. + ** ** These align with the supported feature names[] in print_d_0_eax() for ** values > 1. */ @@ -4370,7 +4421,7 @@ /* 10 => */ "unknown", /* 11 => */ "unknown", /* 12 => */ "unknown", - /* 13 => */ "unknown", + /* 13 => */ "HDC", /* 14 => */ "unknown", /* 15 => */ "unknown", /* 16 => */ "unknown", @@ -4469,6 +4520,7 @@ static named_item names[] = { { "L3 cache allocation technology supported", 1, 1, bools }, { "L2 cache allocation technology supported", 2, 2, bools }, + { "memory bandwidth allocation supported" , 3, 3, bools }, }; print_names(value, names, LENGTH(names, named_item), @@ -4515,6 +4567,8 @@ static named_item names[] = { { "SGX1 supported" , 0, 0, bools }, { "SGX2 supported" , 1, 1, bools }, + { "SGX ENCLV E*VIRTCHILD, ESETCONTEXT" , 5, 5, bools }, + { "SGX ENCLS ETRACKC, ERDINFO, ELDBC, ELDUC", 6, 6, bools }, }; print_names(value, names, LENGTH(names, named_item), @@ -4667,6 +4721,64 @@ } static void +print_18_n_ebx(unsigned int value) +{ + static ccstring parts[] = { /* 0 => */ "soft between logical processors", + /* 1 => */ NULL, + /* 2 => */ NULL, + /* 3 => */ NULL, + /* 4 => */ NULL, + /* 5 => */ NULL, + /* 6 => */ NULL, + /* 7 => */ NULL }; + + static named_item names[] + = { { "4KB page size entries supported" , 0, 0, bools }, + { "2MB page size entries supported" , 1, 1, bools }, + { "4MB page size entries supported" , 2, 2, bools }, + { "1GB page size entries supported" , 3, 3, bools }, + { "partitioning" , 8, 10, parts }, + { "ways of associativity" , 16, 31, NIL_IMAGES }, + }; + + print_names(value, names, LENGTH(names, named_item), + /* max_len => */ 0); +} + +static void +print_18_n_edx(unsigned int value) +{ + static ccstring tlbs[16] = { /* 0000b => */ "invalid (0)", + /* 0001b => */ "data TLB", + /* 0010b => */ "instruction TLB", + /* 0011b => */ "unified TLB", }; + + static named_item names[] + = { { "translation cache type" , 0, 4, tlbs }, + { "translation cache level - 1" , 5, 7, NIL_IMAGES }, + { "fully associative" , 8, 8, bools }, + { "maximum number of addressible IDs" , 14, 25, NIL_IMAGES }, + }; + + print_names(value, names, LENGTH(names, named_item), + /* max_len => */ 0); +} + +static void +print_1b_n_eax(unsigned int value) +{ + static ccstring types[1<<12] = { /* 0 => */ "invalid (0)", + /* 1 => */ "target identifier (1)" }; + + static named_item names[] + = { { "sub-leaf type" , 0, 11, types }, + }; + + print_names(value, names, LENGTH(names, named_item), + /* max_len => */ 0); +} + +static void print_40000002_ecx_xen(unsigned int value) { static named_item names[] @@ -4758,7 +4870,7 @@ = { { "maximum process power state" , 0, 3, NIL_IMAGES }, }; - printf(" hypervisor power management features (0x40000003/ebx):\n"); + printf(" hypervisor power management features (0x40000003/ecx):\n"); print_names(value, names, LENGTH(names, named_item), /* max_len => */ 0); } @@ -4772,7 +4884,7 @@ { "performance monitor support available" , 2, 2, bools }, { "CPU dynamic partitioning events avail" , 3, 3, bools }, { "hypercall XMM input parameters available", 4, 4, bools }, - { "virtual guest idel state available" , 5, 5, bools }, + { "virtual guest idle state available" , 5, 5, bools }, }; printf(" hypervisor feature identification (0x40000003/edx):\n"); @@ -6091,7 +6203,7 @@ printf(" --- cache %d ---\n", try); print_4_eax(words[WORD_EAX]); print_4_ebx(words[WORD_EBX]); - print_4_ecx(words[WORD_EDX]); + print_4_ecx(words[WORD_ECX]); print_4_edx(words[WORD_EDX]); printf(" number of sets - 1 (s) = %u\n", words[WORD_ECX]); @@ -6193,14 +6305,14 @@ print_10_n_eax(words[WORD_EAX]); printf(" Bit-granular map of isolation/contention = 0x%08x\n", words[WORD_EBX]); - print_10_n_ecx(words[WORD_EAX]); - print_10_n_edx(words[WORD_EAX]); + print_10_n_ecx(words[WORD_ECX]); + print_10_n_edx(words[WORD_EDX]); } else { print_reg_raw(reg, try, words); } } else if (reg == 0x12) { if (try == 0) { - printf(" SGX capability (0x12/0):\n"); + printf(" Software Guard Extensions (SGX) capability (0x12/0):\n"); print_12_0_eax(words[WORD_EAX]); print_12_0_ebx(words[WORD_EBX]); print_12_0_edx(words[WORD_EDX]); @@ -6263,6 +6375,21 @@ } else { print_reg_raw(reg, try, words); } + } else if (reg == 0x18) { + printf(" deterministic address translation parameters (0x18/0):\n"); + print_18_n_ebx(words[WORD_EBX]); + printf(" number of sets = 0x%08x (%u)\n", + words[WORD_ECX], words[WORD_ECX]); + print_18_n_edx(words[WORD_EDX]); + } else if (reg == 0x1b) { + printf(" PCONFIG information (0x1b/n):\n"); + print_1b_n_eax(words[WORD_EAX]); + printf(" identifier of target %d = 0x%08x (%u)\n", + 3 * try + 1, words[WORD_EBX], words[WORD_EBX]); + printf(" identifier of target %d = 0x%08x (%u)\n", + 3 * try + 2, words[WORD_ECX], words[WORD_ECX]); + printf(" identifier of target %d = 0x%08x (%u)\n", + 3 * try + 3, words[WORD_EDX], words[WORD_EDX]); } else if (reg == 0x40000000) { // max already set to words[WORD_EAX] printf(" hypervisor_id = \"%-4.4s%-4.4s%-4.4s\"\n", @@ -6895,6 +7022,19 @@ unsigned int try = 0; unsigned int max_tries; for (;;) { + print_header(reg, try, raw); + print_reg(reg, words, raw, try, &stash); + if (try == 0) { + max_tries = words[WORD_EAX]; + } + try++; + if (try > max_tries) break; + real_get(cpuid_fd, reg, words, try, FALSE); + } + } else if (reg == 0x18) { + unsigned int try = 0; + unsigned int max_tries; + for (;;) { print_header(reg, try, raw); print_reg(reg, words, raw, try, &stash); if (try == 0) { diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20170122/cpuid.man new/cpuid-20180419/cpuid.man --- old/cpuid-20170122/cpuid.man 2017-01-22 21:55:39.000000000 +0100 +++ new/cpuid-20180419/cpuid.man 2018-04-19 16:19:57.000000000 +0200 @@ -1,7 +1,7 @@ .\" -.\" $Id: cpuid.man,v 20170122 2017/01/22 13:55:29 todd $ +.\" $Id: cpuid.man,v 20180419 2018/04/19 08:19:45 todd $ .\" -.TH CPUID 1 "22 Jan 2017" "20170122" +.TH CPUID 1 "19 Apr 2018" "20180419" .SH NAME cpuid \- Dump CPUID information for each CPU .SH SYNOPSIS @@ -335,6 +335,7 @@ 324341: Intel Atom Processor N500 Series Specification Update .br Intel 64 Architecture Processor Topology Enumeration (Whitepaper) +by Shih Kuo .br 324456: Intel Celeron Mobile Processor P4000 and U3000 Series Specification Update @@ -429,6 +430,17 @@ 7th Generation Intel Core Processor Families based on U/Y-Processor Line .br 334820: Intel Pentium and Celeron Processor N- and J- Series Specification Update +.br +335718: Intel Xeon Processor E3-1200 v6 Product Family Specification Update +.br +335901: Intel Core X-Series Processor Family Specification Update +.br +336466: 8th Generation Intel Processor Family for S-Processor Platforms +Specification Update +.br +336505: Intel Xeon Processor Scalable Family Specification Update +.br +336562: Intel Pentium Silver and Intel Celeron Processors Specification Update .RE Information on the CPUID instruction and on specific CPUs is available from diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20170122/cpuid.spec new/cpuid-20180419/cpuid.spec --- old/cpuid-20170122/cpuid.spec 2017-01-22 21:56:47.000000000 +0100 +++ new/cpuid-20180419/cpuid.spec 2018-04-19 16:20:19.000000000 +0200 @@ -1,4 +1,4 @@ -%define version 20170122 +%define version 20180419 %define release 1 Summary: dumps CPUID information about the CPU(s) Name: cpuid
