Hello community, here is the log from the commit of package rasdaemon for openSUSE:Factory checked in at 2018-06-22 13:33:37 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/rasdaemon (Old) and /work/SRC/openSUSE:Factory/.rasdaemon.new (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "rasdaemon" Fri Jun 22 13:33:37 2018 rev:9 rq:617739 version:0.6.1 Changes: -------- --- /work/SRC/openSUSE:Factory/rasdaemon/rasdaemon.changes 2018-04-06 17:51:37.526979264 +0200 +++ /work/SRC/openSUSE:Factory/.rasdaemon.new/rasdaemon.changes 2018-06-22 13:33:56.773837750 +0200 @@ -1,0 +2,11 @@ +Fri Jun 15 08:45:26 UTC 2018 - [email protected] + +- Update to version 0.6.1: + * Bump version to 0.6.1 + * rasdaemon: Update DIMM labels for 2-socket servers + * rasdaemon: Add Skylake Xeon MSCOD values + * rasdaemon: ARM: fully initialize ras_arm_event + * Update my email + * mce-intel-p4-p6: prevent build errors with -Werror=format-security + +------------------------------------------------------------------- Old: ---- rasdaemon-0.6.0.tar.xz New: ---- rasdaemon-0.6.1.tar.xz ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ rasdaemon.spec ++++++ --- /var/tmp/diff_new_pack.YOvxDJ/_old 2018-06-22 13:33:57.913795611 +0200 +++ /var/tmp/diff_new_pack.YOvxDJ/_new 2018-06-22 13:33:57.917795463 +0200 @@ -1,7 +1,7 @@ # # spec file for package rasdaemon # -# Copyright (c) 2018 SUSE LINUX Products GmbH, Nuernberg, Germany. +# Copyright (c) 2018 SUSE LINUX GmbH, Nuernberg, Germany. # # All modifications and additions to the file contributed by third parties # remain the property of their copyright owners, unless otherwise agreed @@ -17,12 +17,12 @@ Name: rasdaemon -Version: 0.6.0 +Version: 0.6.1 Release: 0 Summary: Utility to receive RAS error tracings -License: GPL-2.0 +License: GPL-2.0-only Group: Hardware/Other -Url: http://git.infradead.org/users/mchehab/rasdaemon.git +URL: http://git.infradead.org/users/mchehab/rasdaemon.git Source: %{name}-%{version}.tar.xz BuildRequires: autoconf BuildRequires: automake @@ -30,11 +30,11 @@ BuildRequires: libtool BuildRequires: sqlite3-devel BuildRequires: systemd-rpm-macros +Requires: perl-DBD-SQLite +%{?systemd_requires} %ifnarch s390x ppc64le Requires: dmidecode %endif -Requires: perl-DBD-SQLite -%{?systemd_requires} %description rasdaemon is a RAS (Reliability, Availability and Serviceability) logging tool. @@ -58,8 +58,8 @@ --enable-extlog \ --enable-abrt-report \ --enable-arm \ - --enable-non-standard - + --enable-non-standard \ + --enable-hisi-ns-decode make %{?_smp_mflags} V=1 %install @@ -86,7 +86,8 @@ %files %defattr(-,root,root) -%doc AUTHORS ChangeLog COPYING README TODO +%license COPYING +%doc AUTHORS ChangeLog README TODO %{_sbindir}/rasdaemon %{_sbindir}/ras-mc-ctl %{_sbindir}/rcrasdaemon ++++++ _service ++++++ --- /var/tmp/diff_new_pack.YOvxDJ/_old 2018-06-22 13:33:57.949794281 +0200 +++ /var/tmp/diff_new_pack.YOvxDJ/_new 2018-06-22 13:33:57.953794133 +0200 @@ -4,7 +4,7 @@ <param name="scm">git</param> <param name="changesgenerate">enable</param> <param name="filename">rasdaemon</param> - <param name="revision">refs/tags/v0.6.0</param> + <param name="revision">refs/tags/v0.6.1</param> <param name="versionformat">@PARENT_TAG@</param> <param name="versionrewrite-pattern">v(.*)</param> </service> ++++++ _servicedata ++++++ --- /var/tmp/diff_new_pack.YOvxDJ/_old 2018-06-22 13:33:57.969793541 +0200 +++ /var/tmp/diff_new_pack.YOvxDJ/_new 2018-06-22 13:33:57.973793393 +0200 @@ -1,4 +1,4 @@ <servicedata> <service name="tar_scm"> <param name="url">git://git.infradead.org/users/mchehab/rasdaemon.git</param> - <param name="changesrevision">7deef57726d92c8575714be6e9fab100b1edb3bb</param></service></servicedata> \ No newline at end of file + <param name="changesrevision">f47c6addea6990c4a18848bb1d50c1506e836e54</param></service></servicedata> \ No newline at end of file ++++++ rasdaemon-0.6.0.tar.xz -> rasdaemon-0.6.1.tar.xz ++++++ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.6.0/AUTHORS new/rasdaemon-0.6.1/AUTHORS --- old/rasdaemon-0.6.0/AUTHORS 2017-10-14 11:49:59.000000000 +0200 +++ new/rasdaemon-0.6.1/AUTHORS 2018-04-25 12:33:39.000000000 +0200 @@ -1,2 +1,2 @@ -Mauro Carvalho Chehab <[email protected]> +Mauro Carvalho Chehab <[email protected]> diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.6.0/ChangeLog new/rasdaemon-0.6.1/ChangeLog --- old/rasdaemon-0.6.0/ChangeLog 2017-10-14 11:49:59.000000000 +0200 +++ new/rasdaemon-0.6.1/ChangeLog 2018-04-25 12:33:39.000000000 +0200 @@ -1,9 +1,9 @@ -2013-03-12 Mauro Carvalho Chehab <[email protected]> +2013-03-12 Mauro Carvalho Chehab <[email protected]> * Version 0.1.0 * Initial version -2013-05-08 Mauro Carvalho Chehab <[email protected]> +2013-05-08 Mauro Carvalho Chehab <[email protected]> * Version 0.2.0 * Add support to log via syslog @@ -13,7 +13,7 @@ * Add manpages and systemd services * Update to take advantage of tracing features on Kernel 3.10 -2013-05-20 Mauro Carvalho Chehab <[email protected]> +2013-05-20 Mauro Carvalho Chehab <[email protected]> * Version 0.3.0 * Several fixes @@ -21,7 +21,7 @@ * Add support for PCI AER traces * Add a target to build it on rpm-based distros -2013-05-28 Mauro Carvalho Chehab <[email protected]> +2013-05-28 Mauro Carvalho Chehab <[email protected]> * Version 0.4.0 * Several fixes @@ -29,7 +29,7 @@ (requires Kernel 3.10 or upper) * Add memory error decoding on MCE traces -2013-05-29 Mauro Carvalho Chehab <[email protected]> +2013-05-29 Mauro Carvalho Chehab <[email protected]> * Version 0.4.1 * Some fixes, mostly at sqlite3 code @@ -71,7 +71,7 @@ * Enable database recording by default on systemd service file * Correct range while parsing top, middle and lower layers -2015-06-03 Mauro Carvalho Chehab <[email protected]> +2015-06-03 Mauro Carvalho Chehab <[email protected]> - Version 0.5.5 * Improve INSTALL summary instructions @@ -79,7 +79,7 @@ * Add support for Haswell/Broadwell/Knights Landing * Some bug fixes on some MCE handlers -2015-07-03 Mauro Carvalho Chehab <[email protected]> +2015-07-03 Mauro Carvalho Chehab <[email protected]> - Version 0.5.6 * Add internal errors of IA32_MC4_STATUS for Haswell * Use MCA error msg as error_msg @@ -87,23 +87,30 @@ * Remove a space from mcgstatus_msg * Add support to log Local Machine Check Exception (LMCE) -2016-02-05 Mauro Carvalho Chehab <[email protected]> +2016-02-05 Mauro Carvalho Chehab <[email protected]> - Version 0.5.7 * Add model numbers for Broadwell-EP/EX and -DE * Add support for Knights Landing processor -2016-04-15 Mauro Carvalho Chehab <[email protected]> +2016-04-15 Mauro Carvalho Chehab <[email protected]> - Version 0.5.8 * Add Broadwell EP/EX MSCOD and Broadwell DE MSCOD values -2016-06-08 Mauro Carvalho Chehab <[email protected]> +2016-06-08 Mauro Carvalho Chehab <[email protected]> - Version 0.5.9 * Add Knights Mill and updated DELL labels * Configure now reports enabled options -2017-10-14 Mauro Carvalho Chehab <[email protected]> +2017-10-14 Mauro Carvalho Chehab <[email protected]> - Version 0.6.0 * Added support for non-standard CPER error sections * Added support for Hisilicon HIP07 SAS HW module * Added support for ARM events * Updated DIMM labels for Intel Skylake servers + +2018-04-25 Mauro Carvalho Chehab <[email protected]> + - Version 0.6.1 + * Update DIMM labels for 2-socket servers + * Add Skylake Xeon MSCOD values + * ARM: fully initialize ras_arm_event + * Update my email diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.6.0/Makefile.am new/rasdaemon-0.6.1/Makefile.am --- old/rasdaemon-0.6.0/Makefile.am 2017-10-14 11:49:59.000000000 +0200 +++ new/rasdaemon-0.6.1/Makefile.am 2018-04-25 12:33:39.000000000 +0200 @@ -36,7 +36,7 @@ mce-intel-dunnington.c mce-intel-tulsa.c \ mce-intel-sb.c mce-intel-ivb.c mce-intel-haswell.c \ mce-intel-knl.c mce-intel-broadwell-de.c \ - mce-intel-broadwell-epex.c + mce-intel-broadwell-epex.c mce-intel-skylake-xeon.c endif if WITH_EXTLOG rasdaemon_SOURCES += ras-extlog-handler.c diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.6.0/bitfield.c new/rasdaemon-0.6.1/bitfield.c --- old/rasdaemon-0.6.0/bitfield.c 2017-10-14 11:49:59.000000000 +0200 +++ new/rasdaemon-0.6.1/bitfield.c 2018-04-25 12:33:39.000000000 +0200 @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Mauro Carvalho Chehab <[email protected]> + * Copyright (C) 2013 Mauro Carvalho Chehab <[email protected]> * * The code below were adapted from Andi Kleen/Intel/SuSe mcelog code, * released under GNU Public General License, v.2 diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.6.0/configure.ac new/rasdaemon-0.6.1/configure.ac --- old/rasdaemon-0.6.0/configure.ac 2017-10-14 11:49:59.000000000 +0200 +++ new/rasdaemon-0.6.1/configure.ac 2018-04-25 12:33:39.000000000 +0200 @@ -1,4 +1,4 @@ -AC_INIT([RASdaemon], 0.6.0) +AC_INIT([RASdaemon], 0.6.1) AM_SILENT_RULES([yes]) AC_CANONICAL_SYSTEM AC_CONFIG_MACRO_DIR([m4]) diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.6.0/labels/dell new/rasdaemon-0.6.1/labels/dell --- old/rasdaemon-0.6.0/labels/dell 2017-10-14 11:49:59.000000000 +0200 +++ new/rasdaemon-0.6.1/labels/dell 2018-04-25 12:33:39.000000000 +0200 @@ -50,7 +50,7 @@ DIMM_B5: 1.0.1; DIMM_B6: 1.1.1; DIMM_B7: 1.2.1; DIMM_B8: 1.3.1; DIMM_B9: 1.0.2; DIMM_B10: 1.1.2; DIMM_B11: 1.2.2; DIMM_B12: 1.3.2; - Product: PowerEdge R640, PowerEdge R740, PowerEdge R740xd + Product: PowerEdge R640, PowerEdge R740, PowerEdge R740xd, PowerEdge T640 A1: 0.0.0; A2: 0.1.0; A3: 0.2.0; A4: 1.0.0; A5: 1.1.0; A6: 1.2.0; A7: 0.0.1; A8: 0.1.1; A9: 0.2.1; A10: 1.0.1; A11: 1.1.1; A12: 1.2.1; @@ -137,3 +137,16 @@ D1: 6.0.0; D2: 6.1.0; D3: 6.2.0; D4: 7.0.0; D5: 7.1.0; D6: 7.2.0; D7: 6.0.1; D8: 6.1.1; D9: 6.2.1; D10: 7.0.1; D11: 7.1.1; D12: 7.2.1; + + Product: PowerEdge R440, PowerEdge R540 + A1: 0.0.0; A2: 0.1.0; A3: 0.2.0; A4: 1.0.0; A5: 1.1.0; A6: 1.2.0; + A7: 0.0.1; A8: 0.1.1; A9: 1.0.1; A10: 1.1.1; + + B1: 2.0.0; B2: 2.1.0; B3: 2.2.0; B4: 3.0.0; B5: 3.1.0; B6: 3.2.0; + + Product: PowerEdge M640, PowerEdge FC640 + A1: 0.0.0; A2: 0.1.0; A3: 0.2.0; A4: 1.0.0; A5: 1.1.0; A6: 1.2.0; + A7: 0.0.1; A8: 1.0.1; + + B1: 2.0.0; B2: 2.1.0; B3: 2.2.0; B4: 3.0.0; B5: 3.1.0; B6: 3.2.0; + B7: 2.0.1; B8: 3.0.1; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.6.0/man/ras-mc-ctl.8.in new/rasdaemon-0.6.1/man/ras-mc-ctl.8.in --- old/rasdaemon-0.6.0/man/ras-mc-ctl.8.in 2017-10-14 11:49:59.000000000 +0200 +++ new/rasdaemon-0.6.1/man/ras-mc-ctl.8.in 2018-04-25 12:33:39.000000000 +0200 @@ -1,7 +1,7 @@ .\"**************************************************************************** .\" $Id$ .\"**************************************************************************** -.\"Copyright (c) 2013 Mauro Carvalho Chehab <[email protected]> +.\"Copyright (c) 2013 Mauro Carvalho Chehab <[email protected]> .\"This tool is a modification of the edac-ctl, written as part of the .\"edac-utils: .\" Copyright (C) 2006-2007 The Regents of the University of California. diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.6.0/man/rasdaemon.1.in new/rasdaemon-0.6.1/man/rasdaemon.1.in --- old/rasdaemon-0.6.0/man/rasdaemon.1.in 2017-10-14 11:49:59.000000000 +0200 +++ new/rasdaemon-0.6.1/man/rasdaemon.1.in 2018-04-25 12:33:39.000000000 +0200 @@ -1,7 +1,7 @@ .\"**************************************************************************** .\" $Id$ .\"**************************************************************************** -.\"Copyright (c) 2013 Mauro Carvalho Chehab <[email protected]> +.\"Copyright (c) 2013 Mauro Carvalho Chehab <[email protected]> .\" .\" This is free software; you can redistribute it and/or modify it .\" under the terms of the GNU General Public License as published by diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.6.0/mce-amd-k8.c new/rasdaemon-0.6.1/mce-amd-k8.c --- old/rasdaemon-0.6.0/mce-amd-k8.c 2017-10-14 11:49:59.000000000 +0200 +++ new/rasdaemon-0.6.1/mce-amd-k8.c 2018-04-25 12:33:39.000000000 +0200 @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Mauro Carvalho Chehab <[email protected]> + * Copyright (C) 2013 Mauro Carvalho Chehab <[email protected]> * * The code below were adapted from Andi Kleen/Intel/SuSe mcelog code, * released under GNU Public General License, v.2 diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.6.0/mce-intel-p4-p6.c new/rasdaemon-0.6.1/mce-intel-p4-p6.c --- old/rasdaemon-0.6.0/mce-intel-p4-p6.c 2017-10-14 11:49:59.000000000 +0200 +++ new/rasdaemon-0.6.1/mce-intel-p4-p6.c 2018-04-25 12:33:39.000000000 +0200 @@ -127,7 +127,7 @@ for (i = 0; i < ARRAY_SIZE(p4_model); i++) { if (model & (1 << p4_model[i].value)) - mce_snprintf(e->error_msg, p4_model[i].str); + mce_snprintf(e->error_msg, "%s", p4_model[i].str); } } diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.6.0/mce-intel-skylake-xeon.c new/rasdaemon-0.6.1/mce-intel-skylake-xeon.c --- old/rasdaemon-0.6.0/mce-intel-skylake-xeon.c 1970-01-01 01:00:00.000000000 +0100 +++ new/rasdaemon-0.6.1/mce-intel-skylake-xeon.c 2018-04-25 12:33:39.000000000 +0200 @@ -0,0 +1,252 @@ +/* + * The code below came from Tony Luck's mcelog code, + * released under GNU Public General License, v.2 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include <string.h> +#include <stdio.h> + +#include "ras-mce-handler.h" +#include "bitfield.h" + +/* See IA32 SDM Vol3B Table 16-27 */ + +static char *pcu_1[] = { + [0x00] = "No Error", + [0x0d] = "MCA_DMI_TRAINING_TIMEOUT", + [0x0f] = "MCA_DMI_CPU_RESET_ACK_TIMEOUT", + [0x10] = "MCA_MORE_THAN_ONE_LT_AGENT", + [0x1e] = "MCA_BIOS_RST_CPL_INVALID_SEQ", + [0x1f] = "MCA_BIOS_INVALID_PKG_STATE_CONFIG", + [0x25] = "MCA_MESSAGE_CHANNEL_TIMEOUT", + [0x27] = "MCA_MSGCH_PMREQ_CMP_TIMEOUT", + [0x30] = "MCA_PKGC_DIRECT_WAKE_RING_TIMEOUT", + [0x31] = "MCA_PKGC_INVALID_RSP_PCH", + [0x33] = "MCA_PKGC_WATCHDOG_HANG_CBZ_DOWN", + [0x34] = "MCA_PKGC_WATCHDOG_HANG_CBZ_UP", + [0x38] = "MCA_PKGC_WATCHDOG_HANG_C3_UP_SF", + [0x40] = "MCA_SVID_VCCIN_VR_ICC_MAX_FAILURE", + [0x41] = "MCA_SVID_COMMAND_TIMEOUT", + [0x42] = "MCA_SVID_VCCIN_VR_VOUT_FAILURE", + [0x43] = "MCA_SVID_CPU_VR_CAPABILITY_ERROR", + [0x44] = "MCA_SVID_CRITICAL_VR_FAILED", + [0x45] = "MCA_SVID_SA_ITD_ERROR", + [0x46] = "MCA_SVID_READ_REG_FAILED", + [0x47] = "MCA_SVID_WRITE_REG_FAILED", + [0x48] = "MCA_SVID_PKGC_INIT_FAILED", + [0x49] = "MCA_SVID_PKGC_CONFIG_FAILED", + [0x4a] = "MCA_SVID_PKGC_REQUEST_FAILED", + [0x4b] = "MCA_SVID_IMON_REQUEST_FAILED", + [0x4c] = "MCA_SVID_ALERT_REQUEST_FAILED", + [0x4d] = "MCA_SVID_MCP_VR_ABSENT_OR_RAMP_ERROR", + [0x4e] = "MCA_SVID_UNEXPECTED_MCP_VR_DETECTED", + [0x51] = "MCA_FIVR_CATAS_OVERVOL_FAULT", + [0x52] = "MCA_FIVR_CATAS_OVERCUR_FAULT", + [0x58] = "MCA_WATCHDOG_TIMEOUT_PKGC_SLAVE", + [0x59] = "MCA_WATCHDOG_TIMEOUT_PKGC_MASTER", + [0x5a] = "MCA_WATCHDOG_TIMEOUT_PKGS_MASTER", + [0x61] = "MCA_PKGS_CPD_UNCPD_TIMEOUT", + [0x63] = "MCA_PKGS_INVALID_REQ_PCH", + [0x64] = "MCA_PKGS_INVALID_REQ_INTERNAL", + [0x65] = "MCA_PKGS_INVALID_RSP_INTERNAL", + [0x6b] = "MCA_PKGS_SMBUS_VPP_PAUSE_TIMEOUT", + [0x81] = "MCA_RECOVERABLE_DIE_THERMAL_TOO_HOT", +}; + +static struct field pcu_mc4[] = { + FIELD(24, pcu_1), + {} +}; + +/* See IA32 SDM Vol3B Table 16-28 */ + +static char *upi[] = { + [0x00] = "UC Phy Initialization Failure", + [0x01] = "UC Phy detected drift buffer alarm", + [0x02] = "UC Phy detected latency buffer rollover", + [0x10] = "UC LL Rx detected CRC error: unsuccessful LLR: entered abort state", + [0x11] = "UC LL Rx unsupported or undefined packet", + [0x12] = "UC LL or Phy control error", + [0x13] = "UC LL Rx parameter exchange exception", + [0x1F] = "UC LL detected control error from the link-mesh interface", + [0x20] = "COR Phy initialization abort", + [0x21] = "COR Phy reset", + [0x22] = "COR Phy lane failure, recovery in x8 width", + [0x23] = "COR Phy L0c error corrected without Phy reset", + [0x24] = "COR Phy L0c error triggering Phy Reset", + [0x25] = "COR Phy L0p exit error corrected with Phy reset", + [0x30] = "COR LL Rx detected CRC error - successful LLR without Phy Reinit", + [0x31] = "COR LL Rx detected CRC error - successful LLR with Phy Reinit", +}; + +static struct field upi_mc[] = { + FIELD(16, upi), + {} +}; + +/* These apply to MSCOD 0x12 "UC LL or Phy control error" */ +static struct field upi_0x12[] = { + SBITFIELD(22, "Phy Control Error"), + SBITFIELD(23, "Unexpected Retry.Ack flit"), + SBITFIELD(24, "Unexpected Retry.Req flit"), + SBITFIELD(25, "RF parity error"), + SBITFIELD(26, "Routeback Table error"), + SBITFIELD(27, "unexpected Tx Protocol flit (EOP, Header or Data)"), + SBITFIELD(28, "Rx Header-or-Credit BGF credit overflow/underflow"), + SBITFIELD(29, "Link Layer Reset still in progress when Phy enters L0"), + SBITFIELD(30, "Link Layer reset initiated while protocol traffic not idle"), + SBITFIELD(31, "Link Layer Tx Parity Error"), + {} +}; + +/* See IA32 SDM Vol3B Table 16-29 */ + +static struct field mc_bits[] = { + SBITFIELD(16, "Address parity error"), + SBITFIELD(17, "HA write data parity error"), + SBITFIELD(18, "HA write byte enable parity error"), + SBITFIELD(19, "Corrected patrol scrub error"), + SBITFIELD(20, "Uncorrected patrol scrub error"), + SBITFIELD(21, "Corrected spare error"), + SBITFIELD(22, "Uncorrected spare error"), + SBITFIELD(23, "Any HA read error"), + SBITFIELD(24, "WDB read parity error"), + SBITFIELD(25, "DDR4 command address parity error"), + SBITFIELD(26, "Uncorrected address parity error"), + {} +}; + +static char *mc_0x8xx[] = { + [0x0] = "Unrecognized request type", + [0x1] = "Read response to an invalid scoreboard entry", + [0x2] = "Unexpected read response", + [0x3] = "DDR4 completion to an invalid scoreboard entry", + [0x4] = "Completion to an invalid scoreboard entry", + [0x5] = "Completion FIFO overflow", + [0x6] = "Correctable parity error", + [0x7] = "Uncorrectable error", + [0x8] = "Interrupt received while outstanding interrupt was not ACKed", + [0x9] = "ERID FIFO overflow", + [0xa] = "Error on Write credits", + [0xb] = "Error on Read credits", + [0xc] = "Scheduler error", + [0xd] = "Error event", +}; + +static struct field memctrl_mc13[] = { + FIELD(16, mc_0x8xx), + {} +}; + +/* See IA32 SDM Vol3B Table 16-30 */ + +static struct field m2m[] = { + SBITFIELD(16, "MscodDataRdErr"), + SBITFIELD(17, "Reserved"), + SBITFIELD(18, "MscodPtlWrErr"), + SBITFIELD(19, "MscodFullWrErr"), + SBITFIELD(20, "MscodBgfErr"), + SBITFIELD(21, "MscodTimeout"), + SBITFIELD(22, "MscodParErr"), + SBITFIELD(23, "MscodBucket1Err"), + {} +}; + +void skylake_s_decode_model(struct ras_events *ras, struct mce_event *e) +{ + uint64_t status = e->status; + uint32_t mca = status & 0xffff; + unsigned rank0 = -1, rank1 = -1, chan; + + switch (e->bank) { + case 4: + switch (EXTRACT(status, 0, 15) & ~(1ull << 12)) { + case 0x402: case 0x403: + mce_snprintf(e->mcastatus_msg, "Internal errors "); + break; + case 0x406: + mce_snprintf(e->mcastatus_msg, "Intel TXT errors "); + break; + case 0x407: + mce_snprintf(e->mcastatus_msg, "Other UBOX Internal errors "); + break; + } + if (EXTRACT(status, 16, 19)) + mce_snprintf(e->mcastatus_msg, "PCU internal error "); + decode_bitfield(e, status, pcu_mc4); + break; + case 5: + case 12: + case 19: + mce_snprintf(e->mcastatus_msg, "UPI: "); + decode_bitfield(e, status, upi_mc); + if (EXTRACT(status, 16, 21) == 0x12) + decode_bitfield(e, status, upi_0x12); + break; + case 7: case 8: + mce_snprintf(e->mcastatus_msg, "M2M: "); + decode_bitfield(e, status, m2m); + break; + case 13: case 14: case 15: + case 16: case 17: case 18: + mce_snprintf(e->mcastatus_msg, "MemCtrl: "); + if (EXTRACT(status, 27, 27)) + decode_bitfield(e, status, memctrl_mc13); + else + decode_bitfield(e, status, mc_bits); + break; + } + + /* + * Memory error specific code. Returns if the error is not a MC one + */ + + /* Check if the error is at the memory controller */ + if ((mca >> 7) != 1) + return; + + /* Ignore unless this is an corrected extended error from an iMC bank */ + if (e->bank < 13 || e->bank > 18 || (status & MCI_STATUS_UC) || + !test_prefix(7, status & 0xefff)) + return; + + /* + * Parse the reported channel and ranks + */ + + chan = EXTRACT(status, 0, 3); + if (chan == 0xf) + return; + + mce_snprintf(e->mc_location, "memory_channel=%d", chan); + + if (EXTRACT(e->misc, 62, 62)) { + rank0 = EXTRACT(e->misc, 46, 50); + if (EXTRACT(e->misc, 63, 63)) + rank1 = EXTRACT(e->misc, 51, 55); + } + + /* + * FIXME: The conversion from rank to dimm requires to parse the + * DMI tables and call failrank2dimm(). + */ + if (rank0 != -1 && rank1 != -1) + mce_snprintf(e->mc_location, "ranks=%d and %d", + rank0, rank1); + else if (rank0 != -1) + mce_snprintf(e->mc_location, "rank=%d", rank0); +} diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.6.0/mce-intel.c new/rasdaemon-0.6.1/mce-intel.c --- old/rasdaemon-0.6.0/mce-intel.c 2017-10-14 11:49:59.000000000 +0200 +++ new/rasdaemon-0.6.1/mce-intel.c 2018-04-25 12:33:39.000000000 +0200 @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Mauro Carvalho Chehab <[email protected]> + * Copyright (C) 2013 Mauro Carvalho Chehab <[email protected]> * * The code below were adapted from Andi Kleen/Intel/SuSe mcelog code, * released under GNU Public General License, v.2 @@ -408,6 +408,9 @@ case CPU_BROADWELL_EPEX: broadwell_epex_decode_model(ras, e); break; + case CPU_SKYLAKE_XEON: + skylake_s_decode_model(ras, e); + break; default: break; } diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.6.0/misc/rasdaemon.spec.in new/rasdaemon-0.6.1/misc/rasdaemon.spec.in --- old/rasdaemon-0.6.0/misc/rasdaemon.spec.in 2017-10-14 11:49:59.000000000 +0200 +++ new/rasdaemon-0.6.1/misc/rasdaemon.spec.in 2018-04-25 12:33:39.000000000 +0200 @@ -57,22 +57,25 @@ %changelog -* Sat Oct 14 2017 Mauro Carvalho Chehab <[email protected]> 0.6.0-1 -- Bump to version 0.5.8 adding support for Arm and Hisilicon events and update Dell Skylate labels +* Wed Apr 25 2018 Mauro Carvalho Chehab <[email protected]> 0.6.1-1 +- Bump to version 0.6.1 adding support for Skylake Xeon MSCOD, a bug fix and some new DELL labels -* Thu Jun 08 2017 Mauro Carvalho Chehab <[email protected]> 0.5.9-1 -- Bump to version 0.5.8 adding support for Knights Mill and update DELL labels +* Sat Oct 14 2017 Mauro Carvalho Chehab <[email protected]> 0.6.0-1 +- Bump to version 0.6.0 adding support for Arm and Hisilicon events and update Dell Skylate labels -* Fri Apr 15 2016 Mauro Carvalho Chehab <[email protected]> 0.5.8-1 +* Thu Jun 08 2017 Mauro Carvalho Chehab <[email protected]> 0.5.9-1 +- Bump to version 0.5.9 adding support for Knights Mill and update DELL labels + +* Fri Apr 15 2016 Mauro Carvalho Chehab <[email protected]> 0.5.8-1 - Bump to version 0.5.8 adding support for Broadwell EP/EX MSCOD and Broadwell DE MSCOD -* Fri Feb 05 2016 Mauro Carvalho Chehab <[email protected]> 0.5.7-1 +* Fri Feb 05 2016 Mauro Carvalho Chehab <[email protected]> 0.5.7-1 - Bump to version 0.5.7 adding support for Broadwell-EP/EX and -DE and Knights Landing processors -* Fri Jul 03 2015 Mauro Carvalho Chehab <[email protected]> 0.5.6-1 +* Fri Jul 03 2015 Mauro Carvalho Chehab <[email protected]> 0.5.6-1 - Bump to version 0.5.6 with support for LMCE and some fixes -* Wed Jun 03 2015 Mauro Carvalho Chehab <[email protected]> 0.5.5-1 +* Wed Jun 03 2015 Mauro Carvalho Chehab <[email protected]> 0.5.5-1 - Bump to version 0.5.5 with support for newer Intel platforms & some fixes * Fri Aug 15 2014 Mauro Carvalho Chehab <[email protected]> 0.5.4-1 @@ -84,14 +87,14 @@ * Tue Sep 10 2013 Mauro Carvalho Chehab <[email protected]> 0.4.2-1 - Fix ras-mc-ctl layout filling -* Wed May 29 2013 Mauro Carvalho Chehab <[email protected]> 0.4.1-2 +* Wed May 29 2013 Mauro Carvalho Chehab <[email protected]> 0.4.1-2 - Fix the name of perl-DBD-SQLite package -* Wed May 29 2013 Mauro Carvalho Chehab <[email protected]> 0.4.1-1 +* Wed May 29 2013 Mauro Carvalho Chehab <[email protected]> 0.4.1-1 - Updated to version 0.4.1 with contains some bug fixes -* Tue May 28 2013 Mauro Carvalho Chehab <[email protected]> 0.4.0-1 +* Tue May 28 2013 Mauro Carvalho Chehab <[email protected]> 0.4.0-1 - Updated to version 0.4.0 and added support for mce, aer and sqlite3 storage -* Mon May 20 2013 Mauro Carvalho Chehab <[email protected]> 0.3.0-1 +* Mon May 20 2013 Mauro Carvalho Chehab <[email protected]> 0.3.0-1 - Package created diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.6.0/ras-aer-handler.c new/rasdaemon-0.6.1/ras-aer-handler.c --- old/rasdaemon-0.6.0/ras-aer-handler.c 2017-10-14 11:49:59.000000000 +0200 +++ new/rasdaemon-0.6.1/ras-aer-handler.c 2018-04-25 12:33:39.000000000 +0200 @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Mauro Carvalho Chehab <[email protected]> + * Copyright (C) 2013 Mauro Carvalho Chehab <[email protected]> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.6.0/ras-aer-handler.h new/rasdaemon-0.6.1/ras-aer-handler.h --- old/rasdaemon-0.6.0/ras-aer-handler.h 2017-10-14 11:49:59.000000000 +0200 +++ new/rasdaemon-0.6.1/ras-aer-handler.h 2018-04-25 12:33:39.000000000 +0200 @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Mauro Carvalho Chehab <[email protected]> + * Copyright (C) 2013 Mauro Carvalho Chehab <[email protected]> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.6.0/ras-arm-handler.c new/rasdaemon-0.6.1/ras-arm-handler.c --- old/rasdaemon-0.6.0/ras-arm-handler.c 2017-10-14 11:49:59.000000000 +0200 +++ new/rasdaemon-0.6.1/ras-arm-handler.c 2018-04-25 12:33:39.000000000 +0200 @@ -31,6 +31,8 @@ struct tm *tm; struct ras_arm_event ev; + memset(&ev, 0, sizeof(ev)); + /* * Newer kernels (3.10-rc1 or upper) provide an uptime clock. * On previous kernels, the way to properly generate an event would diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.6.0/ras-events.c new/rasdaemon-0.6.1/ras-events.c --- old/rasdaemon-0.6.0/ras-events.c 2017-10-14 11:49:59.000000000 +0200 +++ new/rasdaemon-0.6.1/ras-events.c 2018-04-25 12:33:39.000000000 +0200 @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Mauro Carvalho Chehab <[email protected]> + * Copyright (C) 2013 Mauro Carvalho Chehab <[email protected]> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.6.0/ras-events.h new/rasdaemon-0.6.1/ras-events.h --- old/rasdaemon-0.6.0/ras-events.h 2017-10-14 11:49:59.000000000 +0200 +++ new/rasdaemon-0.6.1/ras-events.h 2018-04-25 12:33:39.000000000 +0200 @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Mauro Carvalho Chehab <[email protected]> + * Copyright (C) 2013 Mauro Carvalho Chehab <[email protected]> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.6.0/ras-mc-handler.c new/rasdaemon-0.6.1/ras-mc-handler.c --- old/rasdaemon-0.6.0/ras-mc-handler.c 2017-10-14 11:49:59.000000000 +0200 +++ new/rasdaemon-0.6.1/ras-mc-handler.c 2018-04-25 12:33:39.000000000 +0200 @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Mauro Carvalho Chehab <[email protected]> + * Copyright (C) 2013 Mauro Carvalho Chehab <[email protected]> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.6.0/ras-mc-handler.h new/rasdaemon-0.6.1/ras-mc-handler.h --- old/rasdaemon-0.6.0/ras-mc-handler.h 2017-10-14 11:49:59.000000000 +0200 +++ new/rasdaemon-0.6.1/ras-mc-handler.h 2018-04-25 12:33:39.000000000 +0200 @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Mauro Carvalho Chehab <[email protected]> + * Copyright (C) 2013 Mauro Carvalho Chehab <[email protected]> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.6.0/ras-mce-handler.c new/rasdaemon-0.6.1/ras-mce-handler.c --- old/rasdaemon-0.6.0/ras-mce-handler.c 2017-10-14 11:49:59.000000000 +0200 +++ new/rasdaemon-0.6.1/ras-mce-handler.c 2018-04-25 12:33:39.000000000 +0200 @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Mauro Carvalho Chehab <[email protected]> + * Copyright (C) 2013 Mauro Carvalho Chehab <[email protected]> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -54,6 +54,7 @@ [CPU_BROADWELL_EPEX] = "Broadwell EP/EX", [CPU_KNIGHTS_LANDING] = "Knights Landing", [CPU_KNIGHTS_MILL] = "Knights Mill", + [CPU_SKYLAKE_XEON] = "Skylake server", }; static enum cputype select_intel_cputype(struct ras_events *ras) @@ -103,6 +104,8 @@ return CPU_KNIGHTS_LANDING; else if (mce->model == 0x85) return CPU_KNIGHTS_MILL; + else if (mce->model == 0x55) + return CPU_SKYLAKE_XEON; if (mce->model > 0x1a) { log(ALL, LOG_INFO, diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.6.0/ras-mce-handler.h new/rasdaemon-0.6.1/ras-mce-handler.h --- old/rasdaemon-0.6.0/ras-mce-handler.h 2017-10-14 11:49:59.000000000 +0200 +++ new/rasdaemon-0.6.1/ras-mce-handler.h 2018-04-25 12:33:39.000000000 +0200 @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Mauro Carvalho Chehab <[email protected]> + * Copyright (C) 2013 Mauro Carvalho Chehab <[email protected]> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -49,6 +49,7 @@ CPU_BROADWELL_EPEX, CPU_KNIGHTS_LANDING, CPU_KNIGHTS_MILL, + CPU_SKYLAKE_XEON, }; struct mce_event { @@ -126,6 +127,7 @@ void tulsa_decode_model(struct mce_event *e); void broadwell_de_decode_model(struct ras_events *ras, struct mce_event *e); void broadwell_epex_decode_model(struct ras_events *ras, struct mce_event *e); +void skylake_s_decode_model(struct ras_events *ras, struct mce_event *e); /* Software defined banks */ #define MCE_EXTENDED_BANK 128 diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.6.0/ras-record.c new/rasdaemon-0.6.1/ras-record.c --- old/rasdaemon-0.6.0/ras-record.c 2017-10-14 11:49:59.000000000 +0200 +++ new/rasdaemon-0.6.1/ras-record.c 2018-04-25 12:33:39.000000000 +0200 @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Mauro Carvalho Chehab <[email protected]> + * Copyright (C) 2013 Mauro Carvalho Chehab <[email protected]> * Copyright (c) 2016, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.6.0/ras-record.h new/rasdaemon-0.6.1/ras-record.h --- old/rasdaemon-0.6.0/ras-record.h 2017-10-14 11:49:59.000000000 +0200 +++ new/rasdaemon-0.6.1/ras-record.h 2018-04-25 12:33:39.000000000 +0200 @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Mauro Carvalho Chehab <[email protected]> + * Copyright (C) 2013 Mauro Carvalho Chehab <[email protected]> * Copyright (c) 2016, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.6.0/rasdaemon.c new/rasdaemon-0.6.1/rasdaemon.c --- old/rasdaemon-0.6.0/rasdaemon.c 2017-10-14 11:49:59.000000000 +0200 +++ new/rasdaemon-0.6.1/rasdaemon.c 2018-04-25 12:33:39.000000000 +0200 @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Mauro Carvalho Chehab <[email protected]> + * Copyright (C) 2013 Mauro Carvalho Chehab <[email protected]> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.6.0/util/ras-mc-ctl.in new/rasdaemon-0.6.1/util/ras-mc-ctl.in --- old/rasdaemon-0.6.0/util/ras-mc-ctl.in 2017-10-14 11:49:59.000000000 +0200 +++ new/rasdaemon-0.6.1/util/ras-mc-ctl.in 2018-04-25 12:33:39.000000000 +0200 @@ -1,7 +1,7 @@ #!/usr/bin/perl -w #****************************************************************************** -# Copyright (c) 2013 Mauro Carvalho Chehab <[email protected]> +# Copyright (c) 2013 Mauro Carvalho Chehab <[email protected]> # # This tool is a modification of the edac-ctl, written as part of the # edac-utils:
