Hello community, here is the log from the commit of package mstflint for openSUSE:Factory checked in at 2018-06-25 11:43:01 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/mstflint (Old) and /work/SRC/openSUSE:Factory/.mstflint.new (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "mstflint" Mon Jun 25 11:43:01 2018 rev:13 rq:618884 version:4.9.0 Changes: -------- --- /work/SRC/openSUSE:Factory/mstflint/mstflint.changes 2018-03-28 10:31:43.944288221 +0200 +++ /work/SRC/openSUSE:Factory/.mstflint.new/mstflint.changes 2018-06-25 11:43:07.511878428 +0200 @@ -1,0 +2,22 @@ +Mon Jun 18 06:31:30 UTC 2018 - [email protected] + +- Update patches to fit science:HPC worflow + - Remove old format patches + - mstflint-4.4.0-implicit-declaration.patch + - mstflint-4.4.0-no-date-time.patch + - mstflint-armv6_arch.patch + - mstflint-armv7_arch.patch + - mstflint-gcc7.patch + - mstflint-s390_arch.patch + - Replaced with new format patches + - Remove-date-time-info-from-build.patch + - Add-s390-s390x-support.patch + - Add-armv6-and-armv7-support.patch + - Fix-gcc7-and-gcc8.patch + - Patch was updated to also fix Gcc8 compilation issues + - Drop obsolete patch + - mstfint-mtcr_ul_no_static_lib.patch +- Update to v4.9.0-3 + - No release notes available + +------------------------------------------------------------------- Old: ---- mstfint-mtcr_ul_no_static_lib.patch mstflint-4.4.0-implicit-declaration.patch mstflint-4.4.0-no-date-time.patch mstflint-armv6_arch.patch mstflint-armv7_arch.patch mstflint-gcc7.patch mstflint-s390_arch.patch New: ---- Add-armv6-and-armv7-support.patch Add-s390-s390x-support.patch Fix-gcc7-and-gcc8.patch Remove-date-time-info-from-build.patch ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ mstflint.spec ++++++ --- /var/tmp/diff_new_pack.82yXfY/_old 2018-06-25 11:43:08.483842580 +0200 +++ /var/tmp/diff_new_pack.82yXfY/_new 2018-06-25 11:43:08.487842432 +0200 @@ -16,39 +16,27 @@ # -%define extra_version -2 +%define extra_version -3 Name: mstflint Version: 4.9.0 Release: 0 Summary: Mellanox Firmware Burning and Diagnostics Tools -License: GPL-2.0 or BSD-2-Clause +License: GPL-2.0-only OR BSD-2-Clause Group: System/Console Url: http://www.openfabrics.org Obsoletes: mstflint-devel < %{version} -Source: https://github.com/Mellanox/mstflint/releases/download/v%{version}-1/mstflint-%{version}.tar.gz -# PATCH-FIX-UPSTREAM Build libmtcr as shared library -Source1: mstfint-mtcr_ul_no_static_lib.patch -# PATCH-FIX-UPSTREAM Add all needed defines to get it built on s390x -Patch1: mstflint-s390_arch.patch -# PATCH-FIX-UPSTREAM implicit declaration of mset_cr_access -Patch2: mstflint-4.4.0-implicit-declaration.patch -# PATCH-FIX-UPSTREAM no __DATE__ and __TIME__ in codes -Patch3: mstflint-4.4.0-no-date-time.patch -# PATCH-FIX-UPSTREAM Add all needed defines to get it built on armv7 -Patch4: mstflint-armv7_arch.patch -# PATCH-FIX-UPSTREAM Ignore fallthrough for GCC7 support -Patch5: mstflint-gcc7.patch -# PATCH-FIX-UPSTREAM Add all needed defines to get it built on armv6 -Patch6: mstflint-armv6_arch.patch - +Source: https://github.com/Mellanox/mstflint/releases/download/v%{version}%{extra_version}/mstflint-%{version}.tar.gz +Patch1: Remove-date-time-info-from-build.patch +Patch2: Add-s390-s390x-support.patch +Patch3: Add-armv6-and-armv7-support.patch +Patch4: Fix-gcc7-and-gcc8.patch BuildRequires: gcc-c++ BuildRequires: infiniband-diags-devel BuildRequires: libibverbs-devel BuildRequires: libtool BuildRequires: zlib-devel BuildRoot: %{_tmppath}/%{name}-%{version}-build -#%%define DT_FLAGS %%{?__commit_date:-D__DATE__=%%__commit_date}' '%%{?__commit_time:-D__TIME__=%%__commit_time}' %description This package contains a burning tool and diagnostic tools for Mellanox @@ -65,8 +53,6 @@ %patch2 %patch3 %patch4 -%patch5 -%patch6 %build ./autogen.sh ++++++ Add-armv6-and-armv7-support.patch ++++++ commit 3178d1cabfcf49959ed196bc599aa13f0a21b3fe Author: Nicolas Morey-Chaisemartin <[email protected]> Date: Thu May 18 11:20:20 2017 +0200 Add armv6 and armv7 support Signed-off-by: Nicolas Morey-Chaisemartin <[email protected]> diff --git common/compatibility.h common/compatibility.h index c034df383ebe..c17eae907d76 100644 --- common/compatibility.h +++ common/compatibility.h @@ -59,6 +59,8 @@ # define ARCH_ppc64 # elif defined(__PPC__) # define ARCH_ppc +# elif defined(__ARM_ARCH_7A__) +# define ARCH_armv7 # elif defined(__aarch64__) # define ARCH_arm64 # elif defined(__arm__) @@ -98,7 +100,7 @@ #define U16H_FMT "0x%04x" #define U8H_FMT "0x%02x" -#if defined(ARCH_x86) || defined(ARCH_ppc) || defined(UEFI_BUILD) || defined(ARCH_arm6l) || defined(ARCH_s390) +#if defined(ARCH_x86) || defined(ARCH_ppc) || defined(UEFI_BUILD) || defined(ARCH_arm6l) || defined(ARCH_s390) || defined(__ARM_ARCH_7A__) # if defined(__MINGW32__) || defined(__MINGW64__) # include <inttypes.h> # define U64D_FMT "0x%" PRId64 diff --git mtcr_ul/packets_common.h mtcr_ul/packets_common.h index 5728fc7fdd6e..213f227d9123 100644 --- mtcr_ul/packets_common.h +++ mtcr_ul/packets_common.h @@ -148,6 +148,8 @@ # define ARCH_ppc64 # elif defined(__PPC__) # define ARCH_ppc +# elif defined(__ARM_ARCH_7A__) +# define ARCH_armv7 # elif defined(__aarch64__) # define ARCH_arm64 # elif defined(__arm__) @@ -178,7 +180,7 @@ # define U8H_FMT "0x%02x" # define U32D_FMT "%u" # define STR_FMT "%s" -#elif defined(ARCH_x86) || defined(ARCH_ppc) || defined(__MINGW32__) || defined(UEFI_BUILD) || defined(ARCH_arm6l) || defined(ARCH_s390) +#elif defined(ARCH_x86) || defined(ARCH_ppc) || defined(__MINGW32__) || defined(UEFI_BUILD) || defined(ARCH_arm6l) || defined(ARCH_s390) || defined(__ARM_ARCH_7A__) # define U64H_FMT "0x%016llx" # define U64D_FMT "%llu" # define U32H_FMT "0x%08x" diff --git tools_layouts/adb_to_c_utils.h tools_layouts/adb_to_c_utils.h index 26adb09bec01..0db09f24c62c 100644 --- tools_layouts/adb_to_c_utils.h +++ tools_layouts/adb_to_c_utils.h @@ -137,6 +137,10 @@ extern "C" { # define ARCH_ppc # elif defined(__aarch64__) # define ARCH_arm64 +# elif defined(__ARM_ARCH_7A__) +# define ARCH_armv7 +# elif defined(__arm__) +# define ARCH_arm6l # elif defined(__s390x__) # define ARCH_s390x # elif defined(__s390__) @@ -177,7 +181,7 @@ extern "C" { # define U64D_FMT "%lu" # define U64H_FMT "0x%016lx" # define U48H_FMT "0x%012lx" -#elif defined(ARCH_x86) || defined(ARCH_ppc) || defined(UEFI_BUILD) || defined(ARCH_s390) +#elif defined(ARCH_x86) || defined(ARCH_ppc) || defined(UEFI_BUILD) || defined(ARCH_s390) || defined(__ARM_ARCH_7A__) || defined(__arm__) # if defined(__MINGW32__) || defined(__MINGW64__) # include <inttypes.h> # define U64D_FMT "0x%" PRId64 ++++++ Add-s390-s390x-support.patch ++++++ commit 1566087c13fa7e9aab45c57f9cf83390e8c0afa6 Author: Nicolas Morey-Chaisemartin <[email protected]> Date: Thu May 18 11:17:54 2017 +0200 Add s390/s390x support Signed-off-by: Nicolas Morey-Chaisemartin <[email protected]> diff --git common/compatibility.h common/compatibility.h index ea320d9ed1da..c034df383ebe 100644 --- common/compatibility.h +++ common/compatibility.h @@ -63,6 +63,10 @@ # define ARCH_arm64 # elif defined(__arm__) # define ARCH_arm6l +# elif defined(__s390x__) +# define ARCH_s390x +# elif defined(__s390__) +# define ARCH_s390 # else # error Unknown CPU architecture using the linux OS # endif @@ -94,7 +98,7 @@ #define U16H_FMT "0x%04x" #define U8H_FMT "0x%02x" -#if defined(ARCH_x86) || defined(ARCH_ppc) || defined(UEFI_BUILD) || defined(ARCH_arm6l) +#if defined(ARCH_x86) || defined(ARCH_ppc) || defined(UEFI_BUILD) || defined(ARCH_arm6l) || defined(ARCH_s390) # if defined(__MINGW32__) || defined(__MINGW64__) # include <inttypes.h> # define U64D_FMT "0x%" PRId64 @@ -109,7 +113,7 @@ # define U48H_FMT "0x%012llx" # define U64D_FMT_GEN "llu" # endif -#elif defined (ARCH_ia64) || defined(ARCH_x86_64) || defined(ARCH_ppc64) || defined(ARCH_arm64) +#elif defined (ARCH_ia64) || defined(ARCH_x86_64) || defined(ARCH_ppc64) || defined(ARCH_arm64) || defined(ARCH_s390x) # define U64D_FMT "%lu" # define U64H_FMT "0x%016lx" # define U48H_FMT "0x%012lx" diff --git mtcr_ul/packets_common.h mtcr_ul/packets_common.h index 453c26fa12f9..5728fc7fdd6e 100644 --- mtcr_ul/packets_common.h +++ mtcr_ul/packets_common.h @@ -152,6 +152,10 @@ # define ARCH_arm64 # elif defined(__arm__) # define ARCH_arm6l +# elif defined(__s390x__) +# define ARCH_s390x +# elif defined(__s390__) +# define ARCH_s390 # else # error Unknown CPU architecture using the linux OS # endif @@ -164,9 +168,9 @@ /**********************************/ /* define macros for print fields */ -//#if defined (ARCH_ia64) || defined(ARCH_x86_64) || defined(ARCH_ppc64) || defined(__MINGW64__) +//#if defined (ARCH_ia64) || defined(ARCH_x86_64) || defined(ARCH_ppc64) || defined(__MINGW64__) || defined(ARCH_s390x) /* -#if !defined(UEFI_BUILD) && (defined (ARCH_ia64) || defined(ARCH_x86_64) || defined(ARCH_ppc64) || defined(__MINGW64__)) +#if !defined(UEFI_BUILD) && (defined (ARCH_ia64) || defined(ARCH_x86_64) || defined(ARCH_ppc64) || defined(__MINGW64__)) || defined(ARCH_s390x) # define U64H_FMT "0x%016lx" # define U64D_FMT "%lu" # define U32H_FMT "0x%08x" @@ -174,7 +178,7 @@ # define U8H_FMT "0x%02x" # define U32D_FMT "%u" # define STR_FMT "%s" -#elif defined(ARCH_x86) || defined(ARCH_ppc) || defined(__MINGW32__) || defined(UEFI_BUILD) || defined(ARCH_arm6l) +#elif defined(ARCH_x86) || defined(ARCH_ppc) || defined(__MINGW32__) || defined(UEFI_BUILD) || defined(ARCH_arm6l) || defined(ARCH_s390) # define U64H_FMT "0x%016llx" # define U64D_FMT "%llu" # define U32H_FMT "0x%08x" diff --git tools_layouts/adb_to_c_utils.h tools_layouts/adb_to_c_utils.h index 6268b69b2e87..26adb09bec01 100644 --- tools_layouts/adb_to_c_utils.h +++ tools_layouts/adb_to_c_utils.h @@ -137,6 +137,10 @@ extern "C" { # define ARCH_ppc # elif defined(__aarch64__) # define ARCH_arm64 +# elif defined(__s390x__) +# define ARCH_s390x +# elif defined(__s390__) +# define ARCH_s390 # else # error Unknown CPU architecture using the linux OS # endif @@ -169,7 +173,11 @@ extern "C" { #define U16H_FMT "0x%04x" #define U8H_FMT "0x%02x" -#if defined(ARCH_x86) || defined(ARCH_ppc) || defined(UEFI_BUILD) +#if defined (ARCH_ia64) || defined(ARCH_x86_64) || defined(ARCH_ppc64) || defined(ARCH_arm64) || defined(ARCH_s390x) +# define U64D_FMT "%lu" +# define U64H_FMT "0x%016lx" +# define U48H_FMT "0x%012lx" +#elif defined(ARCH_x86) || defined(ARCH_ppc) || defined(UEFI_BUILD) || defined(ARCH_s390) # if defined(__MINGW32__) || defined(__MINGW64__) # include <inttypes.h> # define U64D_FMT "0x%" PRId64 @@ -180,10 +188,6 @@ extern "C" { # define U64H_FMT "0x%016llx" # define U48H_FMT "0x%012llx" # endif -#elif defined (ARCH_ia64) || defined(ARCH_x86_64) || defined(ARCH_ppc64) || defined(ARCH_arm64) -# define U64D_FMT "%lu" -# define U64H_FMT "0x%016lx" -# define U48H_FMT "0x%012lx" #else # error Unknown architecture #endif /* ARCH */ ++++++ Fix-gcc7-and-gcc8.patch ++++++ commit eff41e6dc73e6f38e50296d1579372f7527fb84b Author: Nicolas Morey-Chaisemartin <[email protected]> Date: Wed Aug 9 17:31:57 2017 +0200 Fix gcc7 and gcc8 Fix compilation errors for GCC7 and GCC8 Signed-off-by: Nicolas Morey-Chaisemartin <[email protected]> diff --git configure.ac configure.ac index 1aa9d36d5356..ca08a19c8805 100644 --- configure.ac +++ configure.ac @@ -164,16 +164,21 @@ AS_IF([test "x$enable_dynamic_ld" = "xyes"], [ ]) CFLAGS="$CFLAGS -Werror -DMST_UL" +CPPFLAGS="$CPPFLAGS -DMST_UL" CXXFLAGS="$CXXFLAGS -Werror -DMST_UL" AC_CONFIG_FILES( mstflint.spec ) #Check for new ignore flags needed for GCC >= 7 +AX_CHECK_COMPILE_FLAG([-Wno-implicit-fallthrough], [CPPFLAGS="$CPPFLAGS -Wno-implicit-fallthrough"], [], []) +AX_CHECK_COMPILE_FLAG([-Wno-format-overflow], [CPPFLAGS="$CPPFLAGS -Wno-format-overflow"], [], []) +AX_CHECK_COMPILE_FLAG([-Wno-cast-function-type], [CPPFLAGS="$CPPFLAGS -Wno-cast-function-type"], [], []) + +AC_LANG_PUSH([C++]) AX_CHECK_COMPILE_FLAG([-Wno-implicit-fallthrough], [CXXFLAGS="$CXXFLAGS -Wno-implicit-fallthrough"], [], []) -AX_CHECK_COMPILE_FLAG([-Wno-format-overflow], [CFLAGS="$CFLAGS -Wno-format-overflow"], [], []) -AX_CHECK_COMPILE_FLAG([-Wno-implicit-fallthrough], [CFLAGS="$CFLAGS -Wno-implicit-fallthrough"], [], []) AX_CHECK_COMPILE_FLAG([-Wno-format-overflow], [CXXFLAGS="$CXXFLAGS -Wno-format-overflow"], [], []) - +AX_CHECK_COMPILE_FLAG([-Wno-class-memaccess], [CXXFLAGS="$CXXFLAGS -Wno-class-memaccess"], [], []) +AC_LANG_POP([C++]) TOOLS_BUILD_TIME=`date +"%b %d %Y\, %H:%M:%S"` AC_SUBST(TOOLS_BUILD_TIME) ++++++ Remove-date-time-info-from-build.patch ++++++ commit a660f8e5dbc67fefa1b09837d33d986eb1971ec0 Author: Nicolas Morey-Chaisemartin <[email protected]> Date: Thu May 18 07:48:13 2017 +0200 Remove date/time info from build Signed-off-by: Nicolas Morey-Chaisemartin <[email protected]> diff --git common/tools_version.h common/tools_version.h index 7fdb366446ce..dd2f5fb8850d 100644 --- common/tools_version.h +++ common/tools_version.h @@ -70,10 +70,8 @@ int get_version_string(char* buf, int buf_size, const char* exe_name, const char len = snprintf(buf, buf_size, "%s %s, ", exe_name, tool_version); } // cut out first and last "$" from the SVN version string: - len += snprintf(buf + len, buf_size - len, "%s, built on %s, %s. Git SHA Hash: %s", + len += snprintf(buf + len, buf_size - len, "%s, Git SHA Hash: %s", MFT_VERSION_STR, - __DATE__, - __TIME__, TOOLS_GIT_SHA); return len; } ++++++ mstflint-4.9.0.tar.gz ++++++ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mstflint-4.9.0/common/gitversion.h new/mstflint-4.9.0/common/gitversion.h --- old/mstflint-4.9.0/common/gitversion.h 2018-02-27 13:13:11.000000000 +0100 +++ new/mstflint-4.9.0/common/gitversion.h 2018-05-03 15:53:23.000000000 +0200 @@ -1 +1 @@ -#define TOOLS_GIT_SHA "22a6ccd" +#define TOOLS_GIT_SHA "59e7f1c" diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mstflint-4.9.0/kernel/mst.h new/mstflint-4.9.0/kernel/mst.h --- old/mstflint-4.9.0/kernel/mst.h 2018-02-27 13:13:03.000000000 +0100 +++ new/mstflint-4.9.0/kernel/mst.h 2018-05-03 15:52:58.000000000 +0200 @@ -49,6 +49,7 @@ #define MST_VPD_MAGIC 0xD6 +#define PCICONF_MAX_BUFFER_SIZE 256 /****************************************************/ /* GET PARAMS */ #define MST_PARAMS _IOR(MST_PARAMS_MAGIC, 1, struct mst_params) @@ -63,6 +64,7 @@ unsigned int vendor; unsigned int subsystem_device; unsigned int subsystem_vendor; + unsigned int vendor_specific_cap; }; typedef uint32_t u32; @@ -72,16 +74,18 @@ #define MST_READ4 _IOR(MST_BYTE_ACCESS_MAGIC, 1, struct mst_read4_st) struct mst_read4_st { - unsigned int offset; - u32 data; /* OUT */ + unsigned int address_space; + unsigned int offset; + unsigned int data; /*OUT*/ }; #define MST_WRITE4 _IOW(MST_BYTE_ACCESS_MAGIC, 2, struct mst_write4_st) struct mst_write4_st { - unsigned int offset; - u32 data; + unsigned int address_space; + unsigned int offset; + unsigned int data; }; @@ -111,6 +115,21 @@ }; +#define PCICONF_READ4_BUFFER _IOR (MST_BLOCK_ACCESS_MAGIC, 3, struct mst_read4_st) +struct mst_read4_buffer_st { + unsigned int address_space; + unsigned int offset; + int size; + unsigned int data[PCICONF_MAX_BUFFER_SIZE/4]; /*OUT*/ +}; + +#define PCICONF_WRITE4_BUFFER _IOW (MST_BLOCK_ACCESS_MAGIC, 4, struct mst_write4_buffer_st) +struct mst_write4_buffer_st { + unsigned int address_space; + unsigned int offset; + int size; + unsigned int data[PCICONF_MAX_BUFFER_SIZE/4]; /*IN*/ +}; /****************************************************/ /* * INIT / STOP Conf Access diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mstflint-4.9.0/kernel/mst_kernel.h new/mstflint-4.9.0/kernel/mst_kernel.h --- old/mstflint-4.9.0/kernel/mst_kernel.h 2018-02-27 13:13:03.000000000 +0100 +++ new/mstflint-4.9.0/kernel/mst_kernel.h 2018-05-03 15:52:58.000000000 +0200 @@ -87,6 +87,7 @@ struct mst_dev_data { int addr_reg; /* PCICONF address register */ int data_reg; /* PCICONF data register */ + int wo_addr; unsigned int bar; /* PCIMEM bar */ void *hw_addr; /* PCIMEM memory start */ char name[MST_NAME_SIZE]; /* name of character device */ @@ -103,6 +104,10 @@ struct class *cl; unsigned char connectx_wa_slots; /* wa for pci bug */ + /* Vendor specific capability address */ + int vendor_specific_cap; + /* status on VSEC supported spaces*/ + int spaces_support_status; }; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mstflint-4.9.0/kernel/mst_main.c new/mstflint-4.9.0/kernel/mst_main.c --- old/mstflint-4.9.0/kernel/mst_main.c 2018-02-27 13:13:03.000000000 +0100 +++ new/mstflint-4.9.0/kernel/mst_main.c 2018-05-03 15:52:58.000000000 +0200 @@ -40,6 +40,7 @@ #endif #include <linux/pci.h> #include <linux/fs.h> +#include <linux/delay.h> #include "mst_kernel.h" @@ -59,23 +60,433 @@ static struct pci_device_id mst_livefish_pci_table[] = { { PCI_DEVICE(MST_MELLANOX_PCI_VENDOR, 0x01f6) }, /* MT27500 [ConnectX-3 Flash Recovery] */ - { PCI_DEVICE(MST_MELLANOX_PCI_VENDOR, 0x01f8) }, /* MT27520 [ConnectX-3 Pro Flash Recovery] */ + { PCI_DEVICE(MST_MELLANOX_PCI_VENDOR, 0x01f8) }, /* MT27520 [ConnectX-3 Pro Flash Recovery] */ + { PCI_DEVICE(MST_MELLANOX_PCI_VENDOR, 0x01ff) }, /* MT27520 [ConnectX-IB Flash Recovery] */ + { PCI_DEVICE(MST_MELLANOX_PCI_VENDOR, 0x0209) }, /* MT27520 [ConnectX-4 Flash Recovery] */ + { PCI_DEVICE(MST_MELLANOX_PCI_VENDOR, 0x020b) }, /* MT27520 [ConnectX-4Lx Flash Recovery] */ + { PCI_DEVICE(MST_MELLANOX_PCI_VENDOR, 0x020d) }, /* MT27520 [ConnectX-5 Flash Recovery] */ + { PCI_DEVICE(MST_MELLANOX_PCI_VENDOR, 0x0211) }, /* MT27520 [BlueField Flash Recovery] */ { 0, } }; -static struct pci_device_id mst_bar1_pci_table[] = { - { PCI_DEVICE(MST_MELLANOX_PCI_VENDOR, 0x01011) }, /* MT27600 [ConnectX-IB] */ - { PCI_DEVICE(MST_MELLANOX_PCI_VENDOR, 0x01ff) }, /* MT27600 [ConnectX-IB Flash Recovery] */ +static struct pci_device_id mst_bar_pci_table[] = { + { PCI_DEVICE(MST_MELLANOX_PCI_VENDOR, 4099) }, /* MT27600 [ConnectX-3] */ + { PCI_DEVICE(MST_MELLANOX_PCI_VENDOR, 4103) }, /* MT27600 [ConnectX-3Pro] */ { 0, } }; static struct pci_device_id supported_pci_devices[] = { - { PCI_DEVICE(MST_MELLANOX_PCI_VENDOR, 4099) }, /* MT27600 [ConnectX-IB] */ - { PCI_DEVICE(MST_MELLANOX_PCI_VENDOR, 4103) }, /* MT27600 [ConnectX-IB Flash Recovery] */ + { PCI_DEVICE(MST_MELLANOX_PCI_VENDOR, 4099) }, /* MT27600 [ConnectX-3] */ + { PCI_DEVICE(MST_MELLANOX_PCI_VENDOR, 4103) }, /* MT27600 [ConnectX-3Pro] */ + { PCI_DEVICE(MST_MELLANOX_PCI_VENDOR, 4113) }, /* MT27600 [ConnectX-IB] */ + { PCI_DEVICE(MST_MELLANOX_PCI_VENDOR, 4115) }, /* MT27600 [ConnectX-4] */ + { PCI_DEVICE(MST_MELLANOX_PCI_VENDOR, 4117) }, /* MT27600 [ConnectX-4Lx] */ + { PCI_DEVICE(MST_MELLANOX_PCI_VENDOR, 4119) }, /* MT27600 [ConnectX-5] */ + { PCI_DEVICE(MST_MELLANOX_PCI_VENDOR, 4121) }, /* MT27600 [ConnectX-5EX] */ + { PCI_DEVICE(MST_MELLANOX_PCI_VENDOR, 41682) }, /* MT27600 [BlueField] */ { 0, } }; +/****************** VSEC SUPPORT ********************/ + + +// BIT Slicing macros +#define ONES32(size) ((size)?(0xffffffff>>(32-(size))):0) +#define MASK32(offset,size) (ONES32(size)<<(offset)) + +#define EXTRACT_C(source,offset,size) ((((unsigned)(source))>>(offset)) & ONES32(size)) +#define EXTRACT(src,start,len) (((len)==32)?(src):EXTRACT_C(src,start,len)) + +#define MERGE_C(rsrc1,rsrc2,start,len) ((((rsrc2)<<(start)) & (MASK32((start),(len)))) | ((rsrc1) & (~MASK32((start),(len))))) +#define MERGE(rsrc1,rsrc2,start,len) (((len)==32)?(rsrc2):MERGE_C(rsrc1,rsrc2,start,len)) + + +/* Allow minor numbers 0-255 */ +#define MAXMINOR 256 +#define BUFFER_SIZE 256 +#define MLNX_VENDOR_SPECIFIC_CAP_ID 0x9 +#define CRSPACE_DOMAIN 0x2 +#define AS_ICMD 0x3 +#define AS_CR_SPACE 0x2 +#define AS_SEMAPHORE 0xa + +/* PCI address space related enum*/ +enum { + PCI_CAP_PTR = 0x34, + PCI_HDR_SIZE = 0x40, + PCI_EXT_SPACE_ADDR = 0xff, + + PCI_CTRL_OFFSET = 0x4, // for space / semaphore / auto-increment bit + PCI_COUNTER_OFFSET = 0x8, + PCI_SEMAPHORE_OFFSET = 0xc, + PCI_ADDR_OFFSET = 0x10, + PCI_DATA_OFFSET = 0x14, + + PCI_FLAG_BIT_OFFS = 31, + + PCI_SPACE_BIT_OFFS = 0, + PCI_SPACE_BIT_LEN = 16, + + PCI_STATUS_BIT_OFFS = 29, + PCI_STATUS_BIT_LEN = 3, +}; + +/* Mellanox vendor specific enum */ +enum { + CAP_ID = 0x9, + IFC_MAX_RETRIES = 0x10000, + SEM_MAX_RETRIES = 0x1000 +}; + +/* PCI operation enum(read or write)*/ +enum { + READ_OP = 0, + WRITE_OP = 1, +}; + +/* VSEC space status enum*/ +enum { + SS_UNINITIALIZED = 0, + SS_ALL_SPACES_SUPPORTED = 1, + SS_NOT_ALL_SPACES_SUPPORTED = 2 +}; + + +// VSEC supported macro +#define VSEC_FULLY_SUPPORTED(dev) (((dev)->vendor_specific_cap) && ((dev)->spaces_support_status == SS_ALL_SPACES_SUPPORTED)) + + +static int _vendor_specific_sem(struct mst_dev_data *dev, int state) +{ + u32 lock_val; + u32 counter = 0; + int retries = 0; + int ret; + if (!state) {// unlock + ret = pci_write_config_dword(dev->pci_dev, dev->vendor_specific_cap + PCI_SEMAPHORE_OFFSET, 0); + if (ret) return ret; + } else { // lock + do { + if (retries > SEM_MAX_RETRIES) { + return -1; + } + // read semaphore untill 0x0 + ret = pci_read_config_dword(dev->pci_dev, dev->vendor_specific_cap + PCI_SEMAPHORE_OFFSET, &lock_val); + if (ret) return ret; + + if (lock_val) { //semaphore is taken + retries++; + msleep(1); // wait for current op to end + continue; + } + //read ticket + ret = pci_read_config_dword(dev->pci_dev, dev->vendor_specific_cap + PCI_COUNTER_OFFSET, &counter); + if (ret) return ret; + //write ticket to semaphore dword + ret = pci_write_config_dword(dev->pci_dev, dev->vendor_specific_cap + PCI_SEMAPHORE_OFFSET, counter); + if (ret) return ret; + // read back semaphore make sure ticket == semaphore else repeat + ret = pci_read_config_dword(dev->pci_dev, dev->vendor_specific_cap + PCI_SEMAPHORE_OFFSET, &lock_val); + if (ret) return ret; + retries++; + } while (counter != lock_val); + } + return 0; +} + +static int _wait_on_flag(struct mst_dev_data *dev, u8 expected_val) +{ + int retries = 0; + int ret; + u32 flag; + do { + if (retries > IFC_MAX_RETRIES) { + return -1; + } + + ret = pci_read_config_dword(dev->pci_dev, dev->vendor_specific_cap + PCI_ADDR_OFFSET, &flag); + if (ret) return ret; + + flag = EXTRACT(flag, PCI_FLAG_BIT_OFFS, 1); + retries++; + if ((retries & 0xf) == 0) {// dont sleep always + //usleep_range(1,5); + } + } while (flag != expected_val); + return 0; +} + +static int _set_addr_space( struct mst_dev_data *dev, u16 space) +{ + // read modify write + u32 val; + int ret; + ret = pci_read_config_dword(dev->pci_dev, dev->vendor_specific_cap + PCI_CTRL_OFFSET, &val); + if (ret) return ret; + val = MERGE(val, space, PCI_SPACE_BIT_OFFS, PCI_SPACE_BIT_LEN); + ret = pci_write_config_dword(dev->pci_dev, dev->vendor_specific_cap + PCI_CTRL_OFFSET, val); + if (ret) return ret; + // read status and make sure space is supported + ret = pci_read_config_dword(dev->pci_dev, dev->vendor_specific_cap + PCI_CTRL_OFFSET, &val); + if (ret) return ret; + + if (EXTRACT(val, PCI_STATUS_BIT_OFFS, PCI_STATUS_BIT_LEN) == 0) { +// mst_err("CRSPACE %d is not supported !\n", space); + return -1; + } +// mst_err("CRSPACE %d is supported !\n", space); + return 0; +} + +static int _pciconf_rw(struct mst_dev_data *dev, unsigned int offset, u32* data, int rw) +{ + int ret = 0; + u32 address = offset; + + //last 2 bits must be zero as we only allow 30 bits addresses + if (EXTRACT(address, 30, 2)) { + return -1; + } + + address = MERGE(address,(rw ? 1 : 0), PCI_FLAG_BIT_OFFS, 1); + if (rw == WRITE_OP) { + // write data + ret = pci_write_config_dword(dev->pci_dev, dev->vendor_specific_cap + PCI_DATA_OFFSET, *data); + if (ret) return ret; + // write address + ret = pci_write_config_dword(dev->pci_dev, dev->vendor_specific_cap + PCI_ADDR_OFFSET, address); + if (ret) return ret; + // wait on flag + ret = _wait_on_flag(dev, 0); + } else { + // write address + ret = pci_write_config_dword(dev->pci_dev, dev->vendor_specific_cap + PCI_ADDR_OFFSET, address); + if (ret) return ret; + // wait on flag + ret = _wait_on_flag(dev, 1); + // read data + ret = pci_read_config_dword(dev->pci_dev, dev->vendor_specific_cap + PCI_DATA_OFFSET, data); + if (ret) return ret; + } + return ret; +} + +static int _send_pci_cmd_int( struct mst_dev_data *dev, int space, unsigned int offset, u32* data, int rw) +{ + int ret = 0; + + // take semaphore + ret = _vendor_specific_sem(dev, 1); + if (ret) { + return ret; + } + // set address space + ret = _set_addr_space(dev, space); + if (ret) { + goto cleanup; + } + // read/write the data + ret = _pciconf_rw(dev, offset, data, rw); +cleanup: + // clear semaphore + _vendor_specific_sem(dev, 0); + return ret; +} + +static int _block_op( struct mst_dev_data *dev, int space, unsigned int offset, int size, u32* data, int rw) +{ + int i; + int ret = 0; + int wrote_or_read = size; + if (size % 4) { + return -1; + } + // lock semaphore and set address space + ret = _vendor_specific_sem(dev, 1); + if (ret) { + return -1; + } + // set address space + ret = _set_addr_space(dev, space); + if (ret) { + wrote_or_read = -1; + goto cleanup; + } + + for (i = 0; i < size ; i += 4) { + if (_pciconf_rw(dev, offset + i, &(data[(i >> 2)]), rw)) { + wrote_or_read = i; + goto cleanup; + } + } +cleanup: + _vendor_specific_sem(dev, 0); + return wrote_or_read; +} + +static int write4_vsec( struct mst_dev_data *dev, int addresss_domain, unsigned int offset, unsigned int data) +{ + int ret; + + ret = _send_pci_cmd_int(dev, addresss_domain, offset, &data, WRITE_OP); + if (ret) { + return -1; + } + return 0; +} + +static int read4_vsec( struct mst_dev_data *dev, int address_space, unsigned int offset, unsigned int* data) +{ + int ret; + //mst_info("Read from VSEC: offset: %#x\n", offset); + ret = _send_pci_cmd_int(dev, address_space, offset, data, READ_OP); + if (ret) { + return -1; + } + return 0; +} + + + +int pciconf_read4_legacy(struct mst_dev_data *dev, unsigned int offset, unsigned int *data) +{ + int res = 0; + unsigned int new_offset = offset; + //mst_info("pciconf_read4_legacy: offset: %#x\n", offset); + if (dev->type != PCICONF) { + return -1; + } + if (dev->wo_addr) { + new_offset |= 0x1; + } + /* write the wanted address to addr register */ + res = pci_write_config_dword(dev->pci_dev, dev->addr_reg, new_offset); + if (res) { + mst_err("pci_write_config_dword failed\n"); + return res; + } + + /* read the result from data register */ + res = pci_read_config_dword(dev->pci_dev, dev->data_reg, data); + if (res) { + mst_err("pci_read_config_dword failed\n"); + return res; + } + return 0; +} + +int pciconf_write4_legacy(struct mst_dev_data *dev, unsigned int offset, unsigned int data) +{ + int res = 0; + if (dev->type != PCICONF) { + return -1; + } + if (dev->wo_addr) { + /* + * Write operation with new WO GW + * 1. Write data + * 2. Write address + */ + + /* write the data to data register */ + res = pci_write_config_dword(dev->pci_dev, dev->data_reg, data); + if (res) { + mst_err("pci_write_config_dword failed\n"); + return res; + } + /* write the destination address to addr register */ + res = pci_write_config_dword(dev->pci_dev, dev->addr_reg, offset); + if (res) { + mst_err("pci_write_config_dword failed\n"); + return res; + } + + } else { + /* write the destination address to addr register */ + res = pci_write_config_dword(dev->pci_dev, dev->addr_reg, offset); + if (res) { + mst_err("pci_write_conflig_dword failed\n"); + return res; + } + + /* write the data to data register */ + res = pci_write_config_dword(dev->pci_dev, dev->data_reg, data); + if (res) { + mst_err("pci_write_config_dword failed\n"); + return res; + } + } + return 0; +} + + +static int write4_block_vsec( struct mst_dev_data *dev, int address_space, unsigned int offset, int size, u32* data) +{ +// mst_info("HERE %#x %#x %#x\n", address_space, offset, *data); + return _block_op(dev, address_space, offset, size, data, WRITE_OP); +} + +static int read4_block_vsec( struct mst_dev_data *dev, int address_space, unsigned int offset, int size, u32* data) +{ +// mst_info("HERE %#x %#x %#x\n", address_space, offset, *data); + return _block_op(dev, address_space, offset, size, data, READ_OP); +} + +static int get_space_support_status(struct mst_dev_data *dev) +{ + int ret; +// printk("[MST] Checking if the Vendor CAP %d supports the SPACES in devices\n", vend_cap); + if (!dev->vendor_specific_cap) { + return 0; + } + if (dev->spaces_support_status != SS_UNINITIALIZED ) { + return 0; + } + // take semaphore + ret = _vendor_specific_sem(dev, 1); + if (ret) { + mst_err("Failed to lock VSEC semaphore\n"); + return 1; + } + + if( _set_addr_space(dev, AS_CR_SPACE) || + _set_addr_space(dev, AS_ICMD) || + _set_addr_space(dev, AS_SEMAPHORE) ) { + mst_err("At least one SPACE is not supported\n"); + dev->spaces_support_status = SS_NOT_ALL_SPACES_SUPPORTED; + } else { + dev->spaces_support_status = SS_ALL_SPACES_SUPPORTED; + } + // clear semaphore + _vendor_specific_sem(dev, 0); + return 0; +} + + +/********** WO GW ************/ + +#define WO_REG_ADDR_DATA 0xbadacce5 +#define DEVID_OFFSET 0xf0014 +int is_wo_gw(struct pci_dev* pcidev, unsigned addr_reg) +{ + int ret; + unsigned int data = 0; + ret = pci_write_config_dword(pcidev, addr_reg, DEVID_OFFSET); + if (ret) { + return 0; + } + ret = pci_read_config_dword(pcidev, addr_reg, &data); + if (ret) { + return 0; + } + if ( data == WO_REG_ADDR_DATA ) { + return 1; + } + return 0; +} + + /****************************************************/ static int mst_open(struct inode *inode, struct file *file) { @@ -268,7 +679,8 @@ res = -ENODEV; goto fin; } - + // best effort : try to get space spport status if we fail assume we got vsec support. + get_space_support_status(dev); paramst.domain = pci_domain_nr(dev->pci_dev->bus); paramst.bus = dev->pci_dev->bus->number; paramst.slot = PCI_SLOT(dev->pci_dev->devfn); @@ -278,7 +690,14 @@ paramst.vendor = dev->pci_dev->vendor; paramst.subsystem_device = dev->pci_dev->subsystem_device; paramst.subsystem_vendor = dev->pci_dev->subsystem_vendor; - + if (dev->vendor_specific_cap && + (dev->spaces_support_status == SS_ALL_SPACES_SUPPORTED || + dev->spaces_support_status == SS_UNINITIALIZED) ) { + // assume supported if SS_UNINITIALIZED (since semaphore is locked) + paramst.vendor_specific_cap = dev->vendor_specific_cap; + } else { + paramst.vendor_specific_cap = 0; + } if (copy_to_user(user_buf, ¶mst, sizeof(struct mst_params))) { res = -EFAULT; goto fin; @@ -304,19 +723,19 @@ switch (dev->type) { case PCICONF: - /* write the wanted address to addr register */ - res = pci_write_config_dword(dev->pci_dev, dev->addr_reg, readst.offset); - if (res) { - mst_err("pci_write_config_dword failed\n"); - goto fin; - } - - /* read the result from data register */ - res = pci_read_config_dword(dev->pci_dev, dev->data_reg, &out); - if (res) { - mst_err("pci_read_config_dword failed\n"); - goto fin; - } + if (get_space_support_status(dev)) { + res = -EBUSY; + goto fin; + } + + if ( VSEC_FULLY_SUPPORTED(dev) ) { + res = read4_vsec(dev, readst.address_space, readst.offset, &out); + } else { + res = pciconf_read4_legacy(dev, readst.offset, &out); + } + if (res) { + goto fin; + } break; case PCIMEM: @@ -360,19 +779,15 @@ switch (dev->type) { case PCICONF: - /* write the destination address to addr register */ - res = pci_write_config_dword(dev->pci_dev, dev->addr_reg, writest.offset); - if (res) { - mst_err("pci_write_config_dword failed\n"); - goto fin; - } - - /* write the data to data register */ - res = pci_write_config_dword(dev->pci_dev, dev->data_reg, writest.data); - if (res) { - mst_err("pci_write_config_dword failed\n"); - goto fin; - } + if (get_space_support_status(dev)) { + res = -EBUSY; + goto fin; + } + if ( VSEC_FULLY_SUPPORTED(dev) ) { + res = write4_vsec(dev, writest.address_space, writest.offset, writest.data); + } else { + res = pciconf_write4_legacy(dev, writest.offset, writest.data); + } break; case PCIMEM: @@ -497,6 +912,87 @@ break; } + case PCICONF_READ4_BUFFER: + { + struct mst_read4_buffer_st read4_buf; + struct mst_read4_buffer_st* rb_udata = (struct mst_read4_buffer_st *)user_buf; + + if (!dev->initialized) { + mst_err("device is not initialized\n"); + res = -ENODEV; + goto fin; + } + + if (dev->type != PCICONF) { + mst_err("wrong type for device\n"); + res = -EPERM; + goto fin; + } + + if (get_space_support_status(dev)) { + res = -EBUSY; + goto fin; + } + + if (dev->spaces_support_status != SS_ALL_SPACES_SUPPORTED) { + res = -ENOSYS; + goto fin; + } + + + if (copy_from_user(&read4_buf, user_buf, sizeof(read4_buf))) { + res = -EFAULT; + goto fin; + } + + res = read4_block_vsec(dev, read4_buf.address_space, read4_buf.offset, read4_buf.size, read4_buf.data); + if (res != read4_buf.size) { + goto fin; + } + + res = copy_to_user(rb_udata, &read4_buf, sizeof(read4_buf)) ? -EFAULT : read4_buf.size; + goto fin; + } + case PCICONF_WRITE4_BUFFER: + { + struct mst_write4_buffer_st write4_buf; + struct mst_write4_buffer_st* wb_udata = (struct mst_write4_buffer_st *)user_buf; + + if (!dev->initialized) { + mst_err("device is not initialized\n"); + res = -ENODEV; + goto fin; + } + + if (dev->type != PCICONF) { + mst_err("wrong type for device\n"); + res = -EPERM; + goto fin; + } + + + if (get_space_support_status(dev)) { + res = -EBUSY; + goto fin; + } + + if (dev->spaces_support_status != SS_ALL_SPACES_SUPPORTED) { + res = -ENOSYS; + goto fin; + } + + + if (copy_from_user(&write4_buf, user_buf, sizeof(write4_buf))) { + res = -EFAULT; + goto fin; + } + + res = write4_block_vsec(dev, write4_buf.address_space, write4_buf.offset, write4_buf.size, write4_buf.data); + if (res != write4_buf.size) goto fin; + + res = copy_to_user(wb_udata, &write4_buf, sizeof(write4_buf)) ? -EFAULT : write4_buf.size; + goto fin; + } case PCICONF_INIT: { struct mst_pciconf_init_st initst; @@ -520,6 +1016,13 @@ dev->addr_reg = initst.addr_reg; dev->data_reg = initst.data_reg; + + dev->wo_addr = is_wo_gw(dev->pci_dev, initst.addr_reg); + dev->vendor_specific_cap = pci_find_capability(dev->pci_dev, MLNX_VENDOR_SPECIFIC_CAP_ID); + //mst_info("VSEC SUPP: %#x\n", dev->vendor_specific_cap); + dev->spaces_support_status = SS_UNINITIALIZED; // init on first op + + dev->initialized = 1; break; } @@ -810,15 +1313,17 @@ MST_NAME_SIZE, "%s" MST_PCICONF_DEVICE_NAME, dbdf); + + break; case PCIMEM: dev->addr_reg = 0; /* invalid */ dev->data_reg = 0; /* invalid */ - dev->bar = pci_match_id(mst_bar1_pci_table, pdev) ? 1 : 0; + dev->bar = 0; dev->hw_addr = ioremap(pci_resource_start(pdev, dev->bar), MST_MEMORY_SIZE); if (dev->hw_addr <= 0) { - mst_err("could not map device memory\n"); + mst_err("could not map device memory, BAR: %x\n", dev->bar); goto out; } @@ -859,6 +1364,15 @@ cdev_init(&dev->mcdev, &mst_fops); cdev_add(&dev->mcdev, dev->my_dev, 1); //TODO check if cdev_add fails + if (type == PCICONF) { + /* + * Initialize 5th Gen attributes + */ + dev->wo_addr = is_wo_gw(dev->pci_dev, MST_CONF_ADDR_REG); + dev->vendor_specific_cap = pci_find_capability(dev->pci_dev, MLNX_VENDOR_SPECIFIC_CAP_ID); + //mst_info("VSEC SUPP: %#x\n", dev->vendor_specific_cap); + dev->spaces_support_status = SS_UNINITIALIZED; // init on first op + } dev->initialized = 1; list_add_tail(&dev->list, &mst_devices); @@ -936,7 +1450,7 @@ * for livefish devices we only allocate PCICONF * for non livefish both PCICONF and PCIMEM */ - if (!pci_match_id(mst_livefish_pci_table, pdev)) { + if (!pci_match_id(mst_livefish_pci_table, pdev) && pci_match_id(mst_bar_pci_table, pdev)) { /* create new mst_device for PCIMEM */ dev = mst_device_create(PCIMEM, pdev); if (!dev) { Binary files old/mstflint-4.9.0/mlxconfig/mlxconfig_dbs/mlxconfig_host.db and new/mstflint-4.9.0/mlxconfig/mlxconfig_dbs/mlxconfig_host.db differ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mstflint-4.9.0/mstflint.spec new/mstflint-4.9.0/mstflint.spec --- old/mstflint-4.9.0/mstflint.spec 2018-02-27 13:13:18.000000000 +0100 +++ new/mstflint-4.9.0/mstflint.spec 2018-05-03 15:53:34.000000000 +0200 @@ -1,7 +1,7 @@ %{!?ibmadlib: %define ibmadlib libibmad-devel} %{!?name: %define name mstflint} %{!?version: %define version 4.9.0} -%{!?release: %define release 1} +%{!?release: %define release 2} %{!?buildtype: %define buildtype "native"} %{!?noinband: %define noinband 0} %{!?nodc: %define nodc 0} @@ -133,6 +133,9 @@ %{_mandir}/man1/* %changelog +* Sun Apr 1 2018 Adham Masarwah <[email protected]> + Adding support for newer device in Secure Boot kernel and mtcr + * Mon Jul 17 2017 Adham Masarwah <[email protected]> Adding mlxfwreset to mstflint diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mstflint-4.9.0/mstflint.spec.in new/mstflint-4.9.0/mstflint.spec.in --- old/mstflint-4.9.0/mstflint.spec.in 2018-02-27 13:13:03.000000000 +0100 +++ new/mstflint-4.9.0/mstflint.spec.in 2018-05-03 15:52:58.000000000 +0200 @@ -1,7 +1,7 @@ %{!?ibmadlib: %define ibmadlib libibmad-devel} %{!?name: %define name mstflint} %{!?version: %define version 4.9.0} -%{!?release: %define release 1} +%{!?release: %define release 2} %{!?buildtype: %define buildtype "native"} %{!?noinband: %define noinband 0} %{!?nodc: %define nodc 0} @@ -133,6 +133,9 @@ %{_mandir}/man1/* %changelog +* Sun Apr 1 2018 Adham Masarwah <[email protected]> + Adding support for newer device in Secure Boot kernel and mtcr + * Mon Jul 17 2017 Adham Masarwah <[email protected]> Adding mlxfwreset to mstflint diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mstflint-4.9.0/mtcr_ul/mtcr_ul_com.c new/mstflint-4.9.0/mtcr_ul/mtcr_ul_com.c --- old/mstflint-4.9.0/mtcr_ul/mtcr_ul_com.c 2018-02-27 13:13:03.000000000 +0100 +++ new/mstflint-4.9.0/mtcr_ul/mtcr_ul_com.c 2018-05-03 15:52:58.000000000 +0200 @@ -578,12 +578,102 @@ return rc; } +// +// PCI CONF ACCESS FUNCTIONS +// + +#if CONFIG_ENABLE_PCICONF +/* PCI address space related enum*/ +enum { + PCI_CAP_PTR = 0x34, PCI_HDR_SIZE = 0x40, PCI_EXT_SPACE_ADDR = 0xff, + + PCI_CTRL_OFFSET = 0x4, // for space / semaphore / auto-increment bit + PCI_COUNTER_OFFSET = 0x8, + PCI_SEMAPHORE_OFFSET = 0xc, + PCI_ADDR_OFFSET = 0x10, + PCI_DATA_OFFSET = 0x14, + + PCI_FLAG_BIT_OFFS = 31, + + PCI_SPACE_BIT_OFFS = 0, + PCI_SPACE_BIT_LEN = 16, + + PCI_STATUS_BIT_OFFS = 29, + PCI_STATUS_BIT_LEN = 3, +}; + +/* Mellanox vendor specific enum */ +enum { + CAP_ID = 0x9, ICMD_DOMAIN = 0x1, CR_SPACE_DOMAIN = 0x2, SEMAPHORE_DOMAIN = 0xa, IFC_MAX_RETRIES = 2048 +}; + +/* PCI operation enum(read or write)*/ +enum { + READ_OP = 0, WRITE_OP = 1, +}; + +#define READ4_PCI(mf, val_ptr, pci_offs, err_prefix, action_on_fail) \ + do { \ + int rc; \ + int lock_rc; \ + ul_ctx_t *pci_ctx = mf->ul_ctx; \ + lock_rc = _flock_int(pci_ctx->fdlock, LOCK_EX); \ + if (lock_rc) { \ + perror(err_prefix); \ + action_on_fail; \ + } \ + rc = pread(mf->fd, val_ptr, 4, pci_offs); \ + lock_rc = _flock_int(pci_ctx->fdlock, LOCK_UN); \ + if (lock_rc) { \ + perror(err_prefix); \ + action_on_fail; \ + } \ + if (rc != 4 ) { \ + if (rc < 0) \ + perror(err_prefix); \ + action_on_fail; \ + } \ + *val_ptr = __le32_to_cpu(*val_ptr);\ + } while (0) + +#define WRITE4_PCI(mf, val, pci_offs, err_prefix, action_on_fail) \ + do { \ + int rc; \ + int lock_rc; \ + u_int32_t val_le; \ + ul_ctx_t *pci_ctx = mf->ul_ctx; \ + val_le = __cpu_to_le32(val); \ + lock_rc = _flock_int(pci_ctx->fdlock, LOCK_EX); \ + if (lock_rc) { \ + perror(err_prefix); \ + action_on_fail; \ + } \ + rc = pwrite(mf->fd, &val_le, 4, pci_offs); \ + lock_rc = _flock_int(pci_ctx->fdlock, LOCK_UN); \ + if (lock_rc) { \ + perror(err_prefix); \ + action_on_fail; \ + } \ + if (rc != 4 ) { \ + if (rc < 0) \ + perror(err_prefix); \ + action_on_fail; \ + } \ + } while (0) + + +#define WO_REG_ADDR_DATA 0xbadacce5 +#define DEVID_OFFSET 0xf0014 +#define PCICONF_ADDR_OFF 0x58 +#define PCICONF_DATA_OFF 0x5c + + int mtcr_driver_mread4(mfile *mf, unsigned int offset, u_int32_t *value) { int rc = 4; struct mst_read4_st r4; memset(&r4, 0, sizeof(struct mst_read4_st)); - + r4.address_space = (unsigned int)mf->address_space; r4.offset = offset; if ((ioctl(mf->fd, PCICONF_READ4, &r4)) < 0) { rc = -1; @@ -602,6 +692,7 @@ r4.offset = offset; r4.data = value; + r4.address_space = (unsigned int)mf->address_space; if (ioctl(mf->fd, PCICONF_WRITE4, &r4) < 0) { rc = -1; } else { @@ -673,6 +764,69 @@ return length; } +static int driver_mwrite4_block(mfile *mf, unsigned int offset, u_int32_t* data, int length) +{ + if (mf->tp == MST_PCICONF && mf->vsec_supp) { + int left_size = 0; + u_int32_t *dest_ptr = data; + for (left_size = length; left_size > 0; left_size -= PCICONF_MAX_BUFFER_SIZE) { + int towrite; + towrite = (left_size >= PCICONF_MAX_BUFFER_SIZE) ? PCICONF_MAX_BUFFER_SIZE : left_size; + struct mst_write4_buffer_st write4_buf; + memset(&write4_buf, 0, sizeof(write4_buf)); + if (length > (int)sizeof(write4_buf.data)) { + errno = ENOMEM; + return -1; + } + write4_buf.address_space = (unsigned int)mf->address_space; + write4_buf.offset = offset; + write4_buf.size = towrite; + memcpy(write4_buf.data, dest_ptr, towrite); + int ret = ioctl(mf->fd, PCICONF_WRITE4_BUFFER, &write4_buf); + if (ret < 0) { + return -1; + } + offset += towrite; + dest_ptr += towrite; + } + return length; + } else { + + return driver_mwrite_chunk_as_multi_mwrite4(mf, offset, data, length); + } +} + +static int driver_mread4_block(mfile *mf, unsigned int offset, u_int32_t* data, int length) +{ + if (mf->tp == MST_PCICONF && mf->vsec_supp) { + int left_size = 0; + u_int32_t *dest_ptr = data; + for (left_size = length; left_size > 0; left_size -= PCICONF_MAX_BUFFER_SIZE) { + int toread = (left_size >= PCICONF_MAX_BUFFER_SIZE) ? PCICONF_MAX_BUFFER_SIZE : left_size; + + struct mst_read4_buffer_st read4_buf; + memset(&read4_buf, 0, sizeof(read4_buf)); + if (length > (int)sizeof(read4_buf.data)) { + errno = ENOMEM; + return -1; + } + read4_buf.address_space = (unsigned int)mf->address_space; + read4_buf.offset = offset; + read4_buf.size = toread; + int ret = ioctl(mf->fd, PCICONF_READ4_BUFFER, &read4_buf); + if (ret < 0) { + return -1; + } + memcpy(dest_ptr, read4_buf.data, toread); + offset += toread; + dest_ptr += toread; + } + return length; + } else { + return driver_mread_chunk_as_multi_mread4(mf, offset, data, length); + } +} + static int mtcr_driver_mclose(mfile *mf) { @@ -712,17 +866,13 @@ if (mf->fd < 0) { goto end; } - - mf->tp = MST_PCI; - + mf->tp = MST_PCI; ctx->mread4 = mtcr_driver_cr_mread4; ctx->mwrite4 = mtcr_driver_cr_mwrite4; - ctx->mread4_block = driver_mread_chunk_as_multi_mread4; - ctx->mwrite4_block = driver_mwrite_chunk_as_multi_mwrite4; + ctx->mread4_block = driver_mread4_block; + ctx->mwrite4_block = driver_mwrite4_block; ctx->mclose = mtcr_driver_mclose; - - mf->ptr = NULL; - + mf->ptr = NULL; unsigned int slot_num; rc = ioctl(mf->fd, PCI_CONNECTX_WA, &slot_num); if (rc < 0) { @@ -757,11 +907,21 @@ if (mf->fd < 0) { return -1; } + struct mst_params dev_params; + memset(&dev_params, 0, sizeof(dev_params)); + if (ioctl(mf->fd, MST_PARAMS, &dev_params) < 0) { + fprintf(stderr, "-E- Failed to get Device PARAMS!\n"); + return -1; + } + mf->vsec_supp = (int)dev_params.vendor_specific_cap; + if (dev_params.vendor_specific_cap) { + mf->address_space = CR_SPACE_DOMAIN; + } mf->tp = MST_PCICONF; ctx->mread4 = mtcr_driver_mread4; ctx->mwrite4 = mtcr_driver_mwrite4; - ctx->mread4_block = driver_mread_chunk_as_multi_mread4; - ctx->mwrite4_block = driver_mwrite_chunk_as_multi_mwrite4; + ctx->mread4_block = driver_mread4_block; + ctx->mwrite4_block = driver_mwrite4_block; ctx->mclose = mtcr_driver_mclose; init_dev_info_ul(mf, driver_conf_name, domain_p, bus_p, dev_p, func_p); } @@ -769,94 +929,6 @@ return rc; } -// -// PCI CONF ACCESS FUNCTIONS -// - -#if CONFIG_ENABLE_PCICONF -/* PCI address space related enum*/ -enum { - PCI_CAP_PTR = 0x34, PCI_HDR_SIZE = 0x40, PCI_EXT_SPACE_ADDR = 0xff, - - PCI_CTRL_OFFSET = 0x4, // for space / semaphore / auto-increment bit - PCI_COUNTER_OFFSET = 0x8, - PCI_SEMAPHORE_OFFSET = 0xc, - PCI_ADDR_OFFSET = 0x10, - PCI_DATA_OFFSET = 0x14, - - PCI_FLAG_BIT_OFFS = 31, - - PCI_SPACE_BIT_OFFS = 0, - PCI_SPACE_BIT_LEN = 16, - - PCI_STATUS_BIT_OFFS = 29, - PCI_STATUS_BIT_LEN = 3, -}; - -/* Mellanox vendor specific enum */ -enum { - CAP_ID = 0x9, ICMD_DOMAIN = 0x1, CR_SPACE_DOMAIN = 0x2, SEMAPHORE_DOMAIN = 0xa, IFC_MAX_RETRIES = 2048 -}; - -/* PCI operation enum(read or write)*/ -enum { - READ_OP = 0, WRITE_OP = 1, -}; - -#define READ4_PCI(mf, val_ptr, pci_offs, err_prefix, action_on_fail) \ - do { \ - int rc; \ - int lock_rc; \ - ul_ctx_t *pci_ctx = mf->ul_ctx; \ - lock_rc = _flock_int(pci_ctx->fdlock, LOCK_EX); \ - if (lock_rc) { \ - perror(err_prefix); \ - action_on_fail; \ - } \ - rc = pread(mf->fd, val_ptr, 4, pci_offs); \ - lock_rc = _flock_int(pci_ctx->fdlock, LOCK_UN); \ - if (lock_rc) { \ - perror(err_prefix); \ - action_on_fail; \ - } \ - if (rc != 4 ) { \ - if (rc < 0) \ - perror(err_prefix); \ - action_on_fail; \ - } \ - *val_ptr = __le32_to_cpu(*val_ptr);\ - } while (0) - -#define WRITE4_PCI(mf, val, pci_offs, err_prefix, action_on_fail) \ - do { \ - int rc; \ - int lock_rc; \ - u_int32_t val_le; \ - ul_ctx_t *pci_ctx = mf->ul_ctx; \ - val_le = __cpu_to_le32(val); \ - lock_rc = _flock_int(pci_ctx->fdlock, LOCK_EX); \ - if (lock_rc) { \ - perror(err_prefix); \ - action_on_fail; \ - } \ - rc = pwrite(mf->fd, &val_le, 4, pci_offs); \ - lock_rc = _flock_int(pci_ctx->fdlock, LOCK_UN); \ - if (lock_rc) { \ - perror(err_prefix); \ - action_on_fail; \ - } \ - if (rc != 4 ) { \ - if (rc < 0) \ - perror(err_prefix); \ - action_on_fail; \ - } \ - } while (0) - - -#define WO_REG_ADDR_DATA 0xbadacce5 -#define DEVID_OFFSET 0xf0014 -#define PCICONF_ADDR_OFF 0x58 -#define PCICONF_DATA_OFF 0x5c static int is_wo_pciconf_gw(mfile* mf) { diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mstflint-4.9.0/small_utils/mstfwreset.py new/mstflint-4.9.0/small_utils/mstfwreset.py --- old/mstflint-4.9.0/small_utils/mstfwreset.py 2018-02-27 13:13:03.000000000 +0100 +++ new/mstflint-4.9.0/small_utils/mstfwreset.py 2018-05-03 15:52:58.000000000 +0200 @@ -480,6 +480,38 @@ return True if rc == 0 else False +class MlnxPciOpLinuxUl(MlnxPciOpLinux): # Copied from old commit - TODO need to use the same logic of mst load/save + def __init__(self): + super(MlnxPciOpLinuxUl, self).__init__() + self.pciConfSpaceMap = {} + + def savePCIConfigurationSpace(self, devAddr): + confSpaceList = [] + for addr in range(0, 0xff, 4): + if (addr == 0x58 or addr == 0x5c): + confSpaceList.append(0) + continue + val = self.read(devAddr, addr) + confSpaceList.append(val) + self.pciConfSpaceMap[devAddr] = confSpaceList + return + + def loadPCIConfigurationSpace(self, devAddr): + pciConfSpaceList = [] + try: + pciConfSpaceList = self.pciConfSpaceMap[devAddr] + except KeyError as ke: + raise RuntimeError("PCI configuration space for device %s was not saved please reboot server" % devAddr) + if len(pciConfSpaceList) != 64: + raise RuntimeError("PCI configuration space for device %s was not saved properly please reboot server" % devAddr) + for i in range(0, 64): + addr = i * 4 + if (addr == 0x58 or addr == 0x5c): + continue + self.write(devAddr, addr, pciConfSpaceList[i]) + return + + class MlnxPciOpFreeBSD(MlnxPciOp): def __init__(self): @@ -621,7 +653,7 @@ def getPciOpObj(self): operatingSystem = platform.system() if operatingSystem == "Linux": - return MlnxPciOpLinux() + return MlnxPciOpLinuxUl() if IS_MSTFLINT else MlnxPciOpLinux() elif operatingSystem == "FreeBSD": return MlnxPciOpFreeBSD() elif operatingSystem == "Windows": diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mstflint-4.9.0/small_utils/vpd.c new/mstflint-4.9.0/small_utils/vpd.c --- old/mstflint-4.9.0/small_utils/vpd.c 2018-02-27 13:13:03.000000000 +0100 +++ new/mstflint-4.9.0/small_utils/vpd.c 2018-05-03 15:52:58.000000000 +0200 @@ -139,6 +139,7 @@ vpd_t d; int m = 0; int n = 0; + int strict = 0; mfile *mf; vpd_result_t *read_result; vpd_tags_type_t read_type = VPD_ALL; @@ -150,7 +151,7 @@ do { - i=getopt(argc, argv, "mvhnrt:"); + i=getopt(argc, argv, "mvhnsrt:"); if (i<0) { break; } @@ -162,6 +163,9 @@ case 'n': n=1; break; + case 's': + strict = 1; + break; case 'h': rc = 0; goto usage; @@ -220,7 +224,7 @@ if (m) { return fwrite(d, VPD_MAX_SIZE, 1, stdout) != 1; } - rc = mvpd_parse_adv((u_int8_t *)d, VPD_MAX_SIZE, &read_result, read_type, 1, !n); + rc = mvpd_parse_adv((u_int8_t *)d, VPD_MAX_SIZE, &read_result, read_type, strict, !n); if (rc) { fprintf(stderr, "-E- Failed to parse VPD from %s!\n", name); return MVPD_ERR; @@ -247,6 +251,9 @@ printf("-n\tDo not validate check sum.\n"); printf("-r\tDo not check and display the VPD_W tag in the vpd data.\n"); printf("-t ##\tTime out after ## seconds. (Default is 30.)\n\n"); // Currently ignored - for compatibility + // We have also "-s" ("s" for "strict"), which is a hidden flag used by production. + // There are cards out there with inconsistent format, ~200K cards, + // which will cause the tool to fail if this flag is specified. printf("file\tThe PCI id number of the HCA (for example, \"2:00.0\"),\n"); printf("\tthe device name (such as \"mlx4_0\")\n"); printf("\tthe absolute path to the device (\"/sys/class/infiniband/mlx4_0/device\")\n");
