Hello community, here is the log from the commit of package mcelog for openSUSE:Factory checked in at 2019-11-25 11:24:17 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/mcelog (Old) and /work/SRC/openSUSE:Factory/.mcelog.new.26869 (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "mcelog" Mon Nov 25 11:24:17 2019 rev:51 rq:750323 version:1.66 Changes: -------- --- /work/SRC/openSUSE:Factory/mcelog/mcelog.changes 2019-09-25 01:20:17.737795470 +0200 +++ /work/SRC/openSUSE:Factory/.mcelog.new.26869/mcelog.changes 2019-11-25 11:24:18.942105606 +0100 @@ -1,0 +2,14 @@ +Wed Nov 20 14:00:53 UTC 2019 - [email protected] + +- Update to version 1.66 (jira SLE-10087, jira SLE-8853): + * mcelog: Add support for Icelake server, Icelake-D, and Snow Ridge +M email.patch +-> Patched with fuzz, refresh needed + +------------------------------------------------------------------- +Tue Oct 29 15:57:54 UTC 2019 - [email protected] + +- Update to version 1.65: + * mcelog: Add Cascade Lake to supported models + +------------------------------------------------------------------- Old: ---- mcelog-1.64.tar.xz New: ---- mcelog-1.66.tar.xz ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ mcelog.spec ++++++ --- /var/tmp/diff_new_pack.40f5nr/_old 2019-11-25 11:24:19.750105462 +0100 +++ /var/tmp/diff_new_pack.40f5nr/_new 2019-11-25 11:24:19.754105460 +0100 @@ -22,7 +22,7 @@ %endif Name: mcelog -Version: 1.64 +Version: 1.66 Release: 0 Summary: Log Machine Check Events License: GPL-2.0-only ++++++ _service ++++++ --- /var/tmp/diff_new_pack.40f5nr/_old 2019-11-25 11:24:19.810105450 +0100 +++ /var/tmp/diff_new_pack.40f5nr/_new 2019-11-25 11:24:19.810105450 +0100 @@ -5,8 +5,8 @@ <param name="subdir"></param> <param name="filename">mcelog</param> <param name="changesgenerate">enable</param> - <param name="revision">refs/tags/v164</param> - <param name="versionformat">1.64</param> + <param name="revision">refs/tags/v166</param> + <param name="versionformat">1.66</param> <!-- <param name="versionformat">1.64+git%cd.%h</param> --> ++++++ _servicedata ++++++ --- /var/tmp/diff_new_pack.40f5nr/_old 2019-11-25 11:24:19.826105447 +0100 +++ /var/tmp/diff_new_pack.40f5nr/_new 2019-11-25 11:24:19.826105447 +0100 @@ -1,4 +1,4 @@ <servicedata> <service name="tar_scm"> <param name="url">https://github.com/andikleen/mcelog</param> - <param name="changesrevision">e53631f84a181be371c08e0b961180bff77fd2ab</param></service></servicedata> \ No newline at end of file + <param name="changesrevision">ee90ff20ce6a4d5e016aa249ce8b37f359f9fda4</param></service></servicedata> \ No newline at end of file ++++++ email.patch ++++++ --- /var/tmp/diff_new_pack.40f5nr/_old 2019-11-25 11:24:19.850105443 +0100 +++ /var/tmp/diff_new_pack.40f5nr/_new 2019-11-25 11:24:19.850105443 +0100 @@ -7,16 +7,18 @@ msg.c | 8 ++ 6 files changed, 343 insertions(+), 2 deletions(-) ---- mcelog-1.64+git20190805.e53631f.orig/Makefile 2019-09-06 14:06:51.841228190 +0200 -+++ mcelog-1.64+git20190805.e53631f/Makefile 2019-09-06 14:06:56.229228424 +0200 +Index: mcelog-1.66/Makefile +=================================================================== +--- mcelog-1.66.orig/Makefile 2019-11-12 20:05:12.000000000 +0100 ++++ mcelog-1.66/Makefile 2019-11-20 15:22:48.408692817 +0100 @@ -1,3 +1,4 @@ +CONFIG_EMAIL := 1 CFLAGS := -g -Os prefix := /usr etcprefix := -@@ -37,15 +38,23 @@ +@@ -37,15 +38,23 @@ OBJ := p4.o k8.o mcelog.o dmi.o tsc.o co broadwell_de.o broadwell_epex.o skylake_xeon.o \ - denverton.o \ + denverton.o i10nm.o \ msr.o bus.o unknown.o +EMAIL_OBJ := email.o CLEAN := mcelog dmi tsc dbquery .depend .depend.X dbquery.o \ @@ -39,7 +41,7 @@ # dbquery intentionally not installed by default install: mcelog mcelog.conf mcelog.conf.5 mcelog.triggers.5 -@@ -80,7 +89,7 @@ +@@ -80,7 +89,7 @@ dbquery: db.o dbquery.o memutil.o depend: .depend %.o: %.c @@ -48,8 +50,10 @@ version.tmp: FORCE ( printf "char version[] = \"" ; \ +Index: mcelog-1.66/email.c +=================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ mcelog-1.64+git20190805.e53631f/email.c 2019-09-06 14:06:56.229228424 +0200 ++++ mcelog-1.66/email.c 2019-11-20 15:22:48.408692817 +0100 @@ -0,0 +1,200 @@ +#include <unistd.h> +#include <signal.h> @@ -251,8 +255,10 @@ + smtp_destroy_session (session); + return 0; +} +Index: mcelog-1.66/email.h +=================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ mcelog-1.64+git20190805.e53631f/email.h 2019-09-06 14:06:56.229228424 +0200 ++++ mcelog-1.66/email.h 2019-11-20 15:22:48.408692817 +0100 @@ -0,0 +1,34 @@ +#ifndef _MCELOG_EMAIL_H_ +#define _MCELOG_EMAIL_H_ @@ -288,8 +294,10 @@ +#endif + +#endif ---- mcelog-1.64+git20190805.e53631f.orig/mcelog.c 2019-09-06 14:06:51.841228190 +0200 -+++ mcelog-1.64+git20190805.e53631f/mcelog.c 2019-09-06 14:06:56.229228424 +0200 +Index: mcelog-1.66/mcelog.c +=================================================================== +--- mcelog-1.66.orig/mcelog.c 2019-11-12 20:05:12.000000000 +0100 ++++ mcelog-1.66/mcelog.c 2019-11-20 15:22:48.408692817 +0100 @@ -37,6 +37,7 @@ #include <assert.h> #include <signal.h> @@ -308,7 +316,7 @@ enum cputype cputype = CPU_GENERIC; char *logfn = LOG_DEV_FILENAME; -@@ -71,7 +75,7 @@ +@@ -71,7 +75,7 @@ static double cpumhz; static int cpumhz_forced; int ascii_mode; int dump_raw_ascii; @@ -317,7 +325,7 @@ static char *inputfile; char *processor_flags; static int foreground; -@@ -994,6 +998,7 @@ +@@ -1003,6 +1007,7 @@ void usage(void) "--is-cpu-supported Exit with return code indicating whether the CPU is supported\n" "--help Display this message.\n" ); @@ -325,7 +333,7 @@ printf("\n"); print_cputypes(); } -@@ -1063,6 +1068,7 @@ +@@ -1072,6 +1077,7 @@ static struct option options[] = { { "no-imc-log", 0, NULL, O_NO_IMC_LOG }, { "help", 0, NULL, O_HELP }, { "is-cpu-supported", 0, NULL, O_IS_CPU_SUPPORTED }, @@ -333,7 +341,7 @@ {} }; -@@ -1254,11 +1260,86 @@ +@@ -1263,11 +1269,86 @@ static void drop_cred(void) } } @@ -420,7 +428,7 @@ if (recordlen == 0) { Wprintf("no data in mce record\n"); -@@ -1285,12 +1366,16 @@ +@@ -1294,12 +1375,16 @@ static void process(int fd, unsigned rec finish = 1; if (!mce_filter(mce, recordlen)) continue; @@ -437,7 +445,7 @@ flushlog(); } -@@ -1404,6 +1489,8 @@ +@@ -1413,6 +1498,8 @@ int main(int ac, char **av) noargs(ac, av); fprintf(stderr, "mcelog %s\n", MCELOG_VERSION); exit(0); @@ -446,7 +454,7 @@ } else if (opt == 0) break; } -@@ -1438,6 +1525,10 @@ +@@ -1447,6 +1534,10 @@ int main(int ac, char **av) usage(); exit(1); } @@ -457,9 +465,11 @@ checkdmi(); general_setup(); ---- mcelog-1.64+git20190805.e53631f.orig/mcelog.h 2019-09-06 14:06:51.841228190 +0200 -+++ mcelog-1.64+git20190805.e53631f/mcelog.h 2019-09-06 14:06:56.229228424 +0200 -@@ -145,6 +145,7 @@ +Index: mcelog-1.66/mcelog.h +=================================================================== +--- mcelog-1.66.orig/mcelog.h 2019-11-12 20:05:12.000000000 +0100 ++++ mcelog-1.66/mcelog.h 2019-11-20 15:22:48.408692817 +0100 +@@ -148,6 +148,7 @@ enum cputype { enum option_ranges { O_COMMON = 500, O_DISKDB = 1000, @@ -467,8 +477,10 @@ }; enum syslog_opt { ---- mcelog-1.64+git20190805.e53631f.orig/msg.c 2019-09-06 14:06:51.841228190 +0200 -+++ mcelog-1.64+git20190805.e53631f/msg.c 2019-09-06 14:06:56.229228424 +0200 +Index: mcelog-1.66/msg.c +=================================================================== +--- mcelog-1.66.orig/msg.c 2019-11-12 20:05:12.000000000 +0100 ++++ mcelog-1.66/msg.c 2019-11-20 15:22:48.408692817 +0100 @@ -8,10 +8,13 @@ #include "mcelog.h" #include "msg.h" @@ -483,7 +495,7 @@ static char *output_fn; int need_stdout(void) -@@ -135,6 +138,11 @@ +@@ -135,6 +138,11 @@ int Wprintf(char *fmt, ...) n = vfprintf(output_fh ? output_fh : stdout, fmt, ap); va_end(ap); } ++++++ mcelog-1.64.tar.xz -> mcelog-1.66.tar.xz ++++++ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mcelog-1.64/Makefile new/mcelog-1.66/Makefile --- old/mcelog-1.64/Makefile 2019-08-05 20:03:55.000000000 +0200 +++ new/mcelog-1.66/Makefile 2019-11-12 20:05:12.000000000 +0100 @@ -35,7 +35,7 @@ client.o cache.o sysfs.o yellow.o page.o rbtree.o \ sandy-bridge.o ivy-bridge.o haswell.o \ broadwell_de.o broadwell_epex.o skylake_xeon.o \ - denverton.o \ + denverton.o i10nm.o \ msr.o bus.o unknown.o CLEAN := mcelog dmi tsc dbquery .depend .depend.X dbquery.o \ version.o version.c version.tmp diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mcelog-1.64/i10nm.c new/mcelog-1.66/i10nm.c --- old/mcelog-1.64/i10nm.c 1970-01-01 01:00:00.000000000 +0100 +++ new/mcelog-1.66/i10nm.c 2019-11-12 20:05:12.000000000 +0100 @@ -0,0 +1,409 @@ +/* Copyright (C) 2019 Intel Corporation + Decode Intel 10nm specific machine check errors. + + mcelog is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public + License as published by the Free Software Foundation; version + 2. + + mcelog is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should find a copy of v2 of the GNU General Public License somewhere + on your Linux system; if not, write to the Free Software Foundation, + Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + Author: Tony Luck +*/ + +#include "mcelog.h" +#include "bitfield.h" +#include "i10nm.h" +#include "memdb.h" + +/* Memory error was corrected by mirroring with channel failover */ +#define I10NM_MCI_MISC_FO (1ULL<<63) +/* Memory error was corrected by mirroring and primary channel scrubbed successfully */ +#define I10NM_MCI_MISC_MC (1ULL<<62) + +static char *pcu_1[] = { + [0x0D] = "MCA_LLC_BIST_ACTIVE_TIMEOUT", + [0x0E] = "MCA_DMI_TRAINING_TIMEOUT", + [0x0F] = "MCA_DMI_STRAP_SET_ARRIVAL_TIMEOUT", + [0x10] = "MCA_DMI_CPU_RESET_ACK_TIMEOUT", + [0x11] = "MCA_MORE_THAN_ONE_LT_AGENT", + [0x14] = "MCA_INCOMPATIBLE_PCH_TYPE", + [0x1E] = "MCA_BIOS_RST_CPL_INVALID_SEQ", + [0x1F] = "MCA_BIOS_INVALID_PKG_STATE_CONFIG", + [0x2D] = "MCA_PCU_PMAX_CALIB_ERROR", + [0x2E] = "MCA_TSC100_SYNC_TIMEOUT", + [0x3A] = "MCA_GPSB_TIMEOUT", + [0x3B] = "MCA_PMSB_TIMEOUT", + [0x3E] = "MCA_IOSFSB_PMREQ_CMP_TIMEOUT", + [0x40] = "MCA_SVID_VCCIN_VR_ICC_MAX_FAILURE", + [0x42] = "MCA_SVID_VCCIN_VR_VOUT_FAILURE", + [0x43] = "MCA_SVID_CPU_VR_CAPABILITY_ERROR", + [0x44] = "MCA_SVID_CRITICAL_VR_FAILED", + [0x45] = "MCA_SVID_SA_ITD_ERROR", + [0x46] = "MCA_SVID_READ_REG_FAILED", + [0x47] = "MCA_SVID_WRITE_REG_FAILED", + [0x4A] = "MCA_SVID_PKGC_REQUEST_FAILED", + [0x4B] = "MCA_SVID_IMON_REQUEST_FAILED", + [0x4C] = "MCA_SVID_ALERT_REQUEST_FAILED", + [0x4D] = "MCA_SVID_MCP_VR_RAMP_ERROR", + [0x56] = "MCA_FIVR_PD_HARDERR", + [0x58] = "MCA_WATCHDOG_TIMEOUT_PKGC_SLAVE", + [0x59] = "MCA_WATCHDOG_TIMEOUT_PKGC_MASTER", + [0x5A] = "MCA_WATCHDOG_TIMEOUT_PKGS_MASTER", + [0x5B] = "MCA_WATCHDOG_TIMEOUT_MSG_CH_FSM", + [0x5C] = "MCA_WATCHDOG_TIMEOUT_BULK_CR_FSM", + [0x5D] = "MCA_WATCHDOG_TIMEOUT_IOSFSB_FSM", + [0x60] = "MCA_PKGS_SAFE_WP_TIMEOUT", + [0x61] = "MCA_PKGS_CPD_UNCPD_TIMEOUT", + [0x62] = "MCA_PKGS_INVALID_REQ_PCH", + [0x63] = "MCA_PKGS_INVALID_REQ_INTERNAL", + [0x64] = "MCA_PKGS_INVALID_RSP_INTERNAL", + [0x65 ... 0x7A] = "MCA_PKGS_RESET_PREP_TIMEOUT", + [0x7B] = "MCA_PKGS_SMBUS_VPP_PAUSE_TIMEOUT", + [0x7C] = "MCA_PKGS_SMBUS_MCP_PAUSE_TIMEOUT", + [0x7D] = "MCA_PKGS_SMBUS_SPD_PAUSE_TIMEOUT", + [0x80] = "MCA_PKGC_DISP_BUSY_TIMEOUT", + [0x81] = "MCA_PKGC_INVALID_RSP_PCH", + [0x83] = "MCA_PKGC_WATCHDOG_HANG_CBZ_DOWN", + [0x84] = "MCA_PKGC_WATCHDOG_HANG_CBZ_UP", + [0x87] = "MCA_PKGC_WATCHDOG_HANG_C2_BLKMASTER", + [0x88] = "MCA_PKGC_WATCHDOG_HANG_C2_PSLIMIT", + [0x89] = "MCA_PKGC_WATCHDOG_HANG_SETDISP", + [0x8B] = "MCA_PKGC_ALLOW_L1_ERROR", + [0x90] = "MCA_RECOVERABLE_DIE_THERMAL_TOO_HOT", + [0xA0] = "MCA_ADR_SIGNAL_TIMEOUT", + [0xA1] = "MCA_BCLK_FREQ_OC_ABOVE_THRESHOLD", + [0xB0] = "MCA_DISPATCHER_RUN_BUSY_TIMEOUT", +}; + +static char *pcu_2[] = { + [0x04] = "Clock/power IP response timeout", + [0x05] = "SMBus controller raised SMI", + [0x09] = "PM controller received invalid transaction", +}; + +static char *pcu_3[] = { + [0x01] = "Instruction address out of valid space", + [0x02] = "Double bit RAM error on Instruction Fetch", + [0x03] = "Invalid OpCode seen", + [0x04] = "Stack Underflow", + [0x05] = "Stack Overflow", + [0x06] = "Data address out of valid space", + [0x07] = "Double bit RAM error on Data Fetch", +}; + +static struct field pcu1[] = { + FIELD(0, pcu_1), + {} +}; + +static struct field pcu2[] = { + FIELD(0, pcu_2), + {} +}; + +static struct field pcu3[] = { + FIELD(0, pcu_3), + {} +}; + +static struct field upi1[] = { + SBITFIELD(22, "Phy Control Error"), + SBITFIELD(23, "Unexpected Retry.Ack flit"), + SBITFIELD(24, "Unexpected Retry.Req flit"), + SBITFIELD(25, "RF parity error"), + SBITFIELD(26, "Routeback Table error"), + SBITFIELD(27, "Unexpected Tx Protocol flit (EOP, Header or Data)"), + SBITFIELD(28, "Rx Header-or-Credit BGF credit overflow/underflow"), + SBITFIELD(29, "Link Layer Reset still in progress when Phy enters L0"), + SBITFIELD(30, "Link Layer reset initiated while protocol traffic not idle"), + SBITFIELD(31, "Link Layer Tx Parity Error"), + {} +}; + +static char *upi_2[] = { + [0x00] = "Phy Initialization Failure (NumInit)", + [0x01] = "Phy Detected Drift Buffer Alarm", + [0x02] = "Phy Detected Latency Buffer Rollover", + [0x10] = "LL Rx detected CRC error: unsuccessful LLR (entered Abort state)", + [0x11] = "LL Rx Unsupported/Undefined packet", + [0x12] = "LL or Phy Control Error", + [0x13] = "LL Rx Parameter Exception", + [0x1F] = "LL Detected Control Error", + [0x20] = "Phy Initialization Abort", + [0x21] = "Phy Inband Reset", + [0x22] = "Phy Lane failure, recovery in x8 width", + [0x23] = "Phy L0c error corrected without Phy reset", + [0x24] = "Phy L0c error triggering Phy reset", + [0x25] = "Phy L0p exit error corrected with reset", + [0x30] = "LL Rx detected CRC error: successful LLR without Phy Reinit", + [0x31] = "LL Rx detected CRC error: successful LLR with Phy Reinit", + [0x32] = "Tx received LLR", +}; + +static struct field upi2[] = { + FIELD(0, upi_2), + {} +}; + +static struct field m2m[] = { + SBITFIELD(16, "MC read data error"), + SBITFIELD(17, "Reserved"), + SBITFIELD(18, "MC partial write data error"), + SBITFIELD(19, "Full write data error"), + SBITFIELD(20, "M2M clock-domain-crossing buffer (BGF) error"), + SBITFIELD(21, "M2M time out"), + SBITFIELD(22, "M2M tracker parity error"), + SBITFIELD(23, "fatal Bucket1 error"), + {} +}; + +static char *imc_0[] = { + [0x01] = "Address parity error", + [0x02] = "Data parity error", + [0x03] = "Data ECC error", + [0x04] = "Data byte enable parity error", + [0x05] = "Received uncorrectable data", + [0x06] = "Received uncorrectable metadata", + [0x07] = "Transaction ID parity error", + [0x08] = "Corrected patrol scrub error", + [0x10] = "Uncorrected patrol scrub error", + [0x20] = "Corrected spare error", + [0x40] = "Uncorrected spare error", + [0x80] = "Corrected read error", + [0xA0] = "Uncorrected read error", + [0xC0] = "Uncorrected metadata", +}; + +static char *imc_1[] = { + [0x00] = "WDB read parity error", + [0x03] = "RPA parity error", + [0x04] = "RPA parity error", + [0x05] = "WPA parity error", + [0x06] = "DDR_T_DPPP data BE error", + [0x07] = "DDR_T_DPPP data error", + [0x08] = "DDR link failure", + [0x11] = "PCLS CAM error", + [0x12] = "PCLS data error", +}; + +static char *imc_2[] = { + [0x00] = "DDR4 command / address parity error", + [0x20] = "HBM command / address parity error", + [0x21] = "HBM data parity error", +}; + +static char *imc_4[] = { + [0x00] = "RPQ parity (primary) error", + [0x01] = "RPQ parity (buddy) error", + [0x04] = "WPQ parity (primary) error", + [0x05] = "WPQ parity (buddy) error", + [0x08] = "RPB parity (primary) error", + [0x09] = "RPB parity (buddy) error", +}; + +static char *imc_8[] = { + [0x00] = "DDR-T bad request", + [0x01] = "DDR Data response to an invalid entry", + [0x02] = "DDR data response to an entry not expecting data", + [0x03] = "DDR4 completion to an invalid entry", + [0x04] = "DDR-T completion to an invalid entry", + [0x05] = "DDR data/completion FIFO overflow", + [0x06] = "DDR-T ERID correctable parity error", + [0x07] = "DDR-T ERID uncorrectable error", + [0x08] = "DDR-T interrupt received while outstanding interrupt was not ACKed", + [0x09] = "ERID FI FO overflow", + [0x0A] = "DDR-T error on FNV write credits", + [0x0B] = "DDR-T error on FNV read credits", + [0x0C] = "DDR-T scheduler error", + [0x0D] = "DDR-T FNV error event", + [0x0E] = "DDR-T FNV thermal event", + [0x0F] = "CMI packet while idle", + [0x10] = "DDR_T_RPQ_REQ_PARITY_ERR", + [0x11] = "DDR_T_WPQ_REQ_PARITY_ERR", + [0x12] = "2LM_NMFILLWR_CAM_ERR", + [0x13] = "CMI_CREDIT_OVERSUB_ERR", + [0x14] = "CMI_CREDIT_TOTAL_ERR", + [0x15] = "CMI_CREDIT_RSVD_POOL_ERR", + [0x16] = "DDR_T_RD_ERROR", + [0x17] = "WDB_FIFO_ERR", + [0x18] = "CMI_REQ_FIFO_OVERFLOW", + [0x19] = "CMI_REQ_FIFO_UNDERFLOW", + [0x1A] = "CMI_RSP_FIFO_OVERFLOW", + [0x1B] = "CMI_RSP_FIFO_UNDERFLOW", + [0x1C] = "CMI _MISC_MC_CRDT_ERRORS", + [0x1D] = "CMI_MISC_MC_ARB_ERRORS", + [0x1E] = "DDR_T_WR_CMPL_FI FO_OVERFLOW", + [0x1F] = "DDR_T_WR_CMPL_FI FO_UNDERFLOW", + [0x20] = "CMI_RD_CPL_FIFO_OVERFLOW", + [0x21] = "CMI_RD_CPL_FIFO_UNDERFLOW", + [0x22] = "TME_KEY_PAR_ERR", + [0x23] = "TME_CMI_MISC_ERR", + [0x24] = "TME_CMI_OVFL_ERR", + [0x25] = "TME_CMI_UFL_ERR", + [0x26] = "TME_TEM_SECURE_ERR", + [0x27] = "TME_UFILL_PAR_ERR", +}; + +static struct field imc0[] = { + FIELD(0, imc_0), + {} +}; + +static struct field imc1[] = { + FIELD(0, imc_1), + {} +}; + +static struct field imc2[] = { + FIELD(0, imc_2), + {} +}; + +static struct field imc4[] = { + FIELD(0, imc_4), + {} +}; + +static struct field imc8[] = { + FIELD(0, imc_8), + {} +}; + +void i10nm_decode_model(int cputype, int bank, u64 status, u64 misc) +{ + u64 f; + + switch (bank) { + case 4: + Wprintf("PCU: "); + f = EXTRACT(status, 24, 31); + if (f) + decode_bitfield(f, pcu1); + f = EXTRACT(status, 20, 23); + if (f) + decode_bitfield(f, pcu2); + f = EXTRACT(status, 16, 19); + if (f) + decode_bitfield(f, pcu3); + break; + + case 5: + case 7: + case 8: + Wprintf("UPI: "); + f = EXTRACT(status, 22, 31); + if (f) + decode_bitfield(status, upi1); + f = EXTRACT(status, 16, 21); + decode_bitfield(f, upi2); + break; + + case 12: + case 16: + case 20: + case 24: + Wprintf("M2M: "); + f = EXTRACT(status, 24, 25); + Wprintf("MscodDDRType=0x%llx\n", f); + f = EXTRACT(status, 26, 31); + Wprintf("MscodMiscErrs=0x%llx\n", f); + decode_bitfield(status, m2m); + break; + + case 13: + case 14: + case 15: + case 17: + case 18: + case 19: + case 21: + case 22: + case 23: + case 25: + case 26: + case 27: + Wprintf("MemCtrl: "); + f = EXTRACT(status, 16, 23); + switch (EXTRACT(status, 24, 31)) { + case 0: decode_bitfield(f, imc0); break; + case 1: decode_bitfield(f, imc1); break; + case 2: decode_bitfield(f, imc2); break; + case 4: decode_bitfield(f, imc4); break; + case 8: decode_bitfield(f, imc8); break; + } + break; + } +} + +int i10nm_ce_type(int bank, u64 status, u64 misc) +{ + if (bank != 12 && bank != 16 && bank != 20 && bank != 24) + return 0; + + if (status & MCI_STATUS_MISCV) { + if (misc & I10NM_MCI_MISC_FO) + return 1; + if (misc & I10NM_MCI_MISC_MC) + return 2; + } + + return 0; +} + +/* + * There isn't enough information to identify the DIMM. But + * we can derive the channel from the bank number. + * There can be four memory controllers with two channels each. + */ +void i10nm_memerr_misc(struct mce *m, int *channel, int *dimm) +{ + u64 status = m->status; + unsigned int chan, imc; + + /* Check this is a memory error */ + if (!test_prefix(7, status & 0xefff)) + return; + + chan = EXTRACT(status, 0, 3); + if (chan == 0xf) + return; + + switch (m->bank) { + case 12: /* M2M 0 */ + case 13: /* IMC 0, Channel 0 */ + case 14: /* IMC 0, Channel 1 */ + case 15: /* IMC 0, Channel 2 */ + imc = 0; + break; + case 16: /* M2M 1 */ + case 17: /* IMC 1, Channel 0 */ + case 18: /* IMC 1, Channel 1 */ + case 19: /* IMC 1, Channel 2 */ + imc = 1; + break; + case 20: /* M2M 2 */ + case 21: /* IMC 2, Channel 0 */ + case 22: /* IMC 2, Channel 1 */ + case 23: /* IMC 2, Channel 2 */ + imc = 2; + break; + case 24: /* M2M 3 */ + case 25: /* IMC 3, Channel 0 */ + case 26: /* IMC 3, Channel 1 */ + case 27: /* IMC 3, Channel 2 */ + imc = 3; + break; + default: + return; + } + + channel[0] = imc * 3 + chan; +} diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mcelog-1.64/i10nm.h new/mcelog-1.66/i10nm.h --- old/mcelog-1.64/i10nm.h 1970-01-01 01:00:00.000000000 +0100 +++ new/mcelog-1.66/i10nm.h 2019-11-12 20:05:12.000000000 +0100 @@ -0,0 +1,3 @@ +void i10nm_decode_model(int cputype, int bank, u64 status, u64 misc); +int i10nm_ce_type(int bank, u64 status, u64 misc); +void i10nm_memerr_misc(struct mce *m, int *channel, int *dimm); diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mcelog-1.64/intel.c new/mcelog-1.66/intel.c --- old/mcelog-1.64/intel.c 2019-08-05 20:03:55.000000000 +0200 +++ new/mcelog-1.66/intel.c 2019-11-12 20:05:12.000000000 +0100 @@ -26,6 +26,7 @@ #include "ivy-bridge.h" #include "haswell.h" #include "skylake_xeon.h" +#include "i10nm.h" int memory_error_support; @@ -38,7 +39,9 @@ cpu == CPU_BROADWELL_DE || cpu == CPU_BROADWELL_EPEX || cpu == CPU_KNIGHTS_LANDING || cpu == CPU_KNIGHTS_MILL || cpu == CPU_SKYLAKE || cpu == CPU_SKYLAKE_XEON || - cpu == CPU_KABYLAKE || cpu == CPU_DENVERTON || cpu == CPU_ICELAKE) + cpu == CPU_KABYLAKE || cpu == CPU_DENVERTON || cpu == CPU_ICELAKE || + cpu == CPU_ICELAKE_XEON || cpu == CPU_ICELAKE_DE || + cpu == CPU_TREMONT_D) memory_error_support = 1; } @@ -101,6 +104,12 @@ return CPU_DENVERTON; else if (model == 0x7D || model == 0x7E || model == 0x9D) return CPU_ICELAKE; + else if (model == 0x6A) + return CPU_ICELAKE_XEON; + else if (model == 0x6C) + return CPU_ICELAKE_DE; + else if (model == 0x86) + return CPU_TREMONT_D; if (model > 0x1a) { Eprintf("Family 6 Model %u CPU: only decoding architectural errors\n", model); @@ -150,6 +159,11 @@ case CPU_SKYLAKE_XEON: skylake_memerr_misc(m, channel, dimm); break; + case CPU_ICELAKE_XEON: + case CPU_ICELAKE_DE: + case CPU_TREMONT_D: + i10nm_memerr_misc(m, channel, dimm); + break; default: break; } diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mcelog-1.64/intel.h new/mcelog-1.66/intel.h --- old/mcelog-1.64/intel.h 2019-08-05 20:03:55.000000000 +0200 +++ new/mcelog-1.66/intel.h 2019-11-12 20:05:12.000000000 +0100 @@ -29,5 +29,8 @@ case CPU_SKYLAKE: \ case CPU_SKYLAKE_XEON: \ case CPU_KABYLAKE: \ - case CPU_DENVERTON + case CPU_DENVERTON: \ + case CPU_ICELAKE_XEON: \ + case CPU_ICELAKE_DE: \ + case CPU_TREMONT_D diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mcelog-1.64/mcelog.c new/mcelog-1.66/mcelog.c --- old/mcelog-1.64/mcelog.c 2019-08-05 20:03:55.000000000 +0200 +++ new/mcelog-1.66/mcelog.c 2019-11-12 20:05:12.000000000 +0100 @@ -245,6 +245,9 @@ [CPU_KABYLAKE] = "Kabylake", [CPU_DENVERTON] = "Denverton", [CPU_ICELAKE] = "Icelake", + [CPU_ICELAKE_XEON] = "Icelake server", + [CPU_ICELAKE_DE] = "Icelake server D Family", + [CPU_TREMONT_D] = "Tremont microserver", }; static struct config_choice cpu_choices[] = { @@ -295,8 +298,12 @@ { "atom", CPU_ATOM }, { "skylake", CPU_SKYLAKE }, { "skylake_server", CPU_SKYLAKE_XEON }, + { "cascadelake_server", CPU_SKYLAKE_XEON }, { "kabylake", CPU_KABYLAKE }, { "denverton", CPU_DENVERTON }, + { "icelake_server", CPU_ICELAKE_XEON }, + { "icelake-d", CPU_ICELAKE_DE }, + { "snowridge", CPU_TREMONT_D }, { NULL } }; @@ -468,7 +475,9 @@ cputype != CPU_BROADWELL_DE && cputype != CPU_BROADWELL_EPEX && cputype != CPU_KNIGHTS_LANDING && cputype != CPU_KNIGHTS_MILL && cputype != CPU_SKYLAKE && cputype != CPU_SKYLAKE_XEON && - cputype != CPU_KABYLAKE && cputype != CPU_DENVERTON) + cputype != CPU_KABYLAKE && cputype != CPU_DENVERTON && + cputype != CPU_ICELAKE_XEON && cputype != CPU_ICELAKE_DE && + cputype != CPU_TREMONT_D) resolveaddr(m->addr); } diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mcelog-1.64/mcelog.h new/mcelog-1.66/mcelog.h --- old/mcelog-1.64/mcelog.h 2019-08-05 20:03:55.000000000 +0200 +++ new/mcelog-1.66/mcelog.h 2019-11-12 20:05:12.000000000 +0100 @@ -140,6 +140,9 @@ CPU_KABYLAKE, CPU_DENVERTON, CPU_ICELAKE, + CPU_ICELAKE_XEON, + CPU_ICELAKE_DE, + CPU_TREMONT_D, }; enum option_ranges { diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/mcelog-1.64/p4.c new/mcelog-1.66/p4.c --- old/mcelog-1.64/p4.c 2019-08-05 20:03:55.000000000 +0200 +++ new/mcelog-1.66/p4.c 2019-11-12 20:05:12.000000000 +0100 @@ -40,6 +40,7 @@ #include "broadwell_epex.h" #include "skylake_xeon.h" #include "denverton.h" +#include "i10nm.h" /* decode mce for P4/Xeon and Core2 family */ @@ -306,6 +307,8 @@ return bdw_epex_ce_type(bank, status, misc); case CPU_SKYLAKE_XEON: return skylake_s_ce_type(bank, status, misc); + case CPU_ICELAKE_XEON: + return i10nm_ce_type(bank, status, misc); default: return 0; } @@ -453,6 +456,11 @@ case CPU_SKYLAKE_XEON: skylake_s_decode_model(cputype, log->bank, log->status, log->misc); break; + case CPU_ICELAKE_XEON: + case CPU_ICELAKE_DE: + case CPU_TREMONT_D: + i10nm_decode_model(cputype, log->bank, log->status, log->misc); + break; case CPU_DENVERTON: denverton_decode_model(cputype, log->bank, log->status, log->misc); break;
