Hello community, here is the log from the commit of package llvm9 for openSUSE:Factory checked in at 2020-01-06 16:01:44 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/llvm9 (Old) and /work/SRC/openSUSE:Factory/.llvm9.new.6675 (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "llvm9" Mon Jan 6 16:01:44 2020 rev:6 rq:760817 version:9.0.1 Changes: -------- --- /work/SRC/openSUSE:Factory/llvm9/llvm9.changes 2019-12-25 10:54:50.101629934 +0100 +++ /work/SRC/openSUSE:Factory/.llvm9.new.6675/llvm9.changes 2020-01-06 16:01:50.213714848 +0100 @@ -1,0 +2,8 @@ +Fri Jan 3 15:28:52 UTC 2020 - Andreas Schwab <[email protected]> + +- Enable support for riscv64 +- clang-riscv64-rv64gc.diff, riscv64-suse-linux.patch, + llvm-riscv64-fix-cffi.diff, D60657-riscv-pcrel_lo.diff: Backports from + master + +------------------------------------------------------------------- New: ---- D60657-riscv-pcrel_lo.diff clang-riscv64-rv64gc.diff llvm-riscv64-fix-cffi.diff riscv64-suse-linux.patch ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ llvm9.spec ++++++ --- /var/tmp/diff_new_pack.Q6xWzO/_old 2020-01-06 16:01:53.105716352 +0100 +++ /var/tmp/diff_new_pack.Q6xWzO/_new 2020-01-06 16:01:53.109716354 +0100 @@ -1,7 +1,7 @@ # # spec file for package llvm9 # -# Copyright (c) 2019 SUSE LLC +# Copyright (c) 2020 SUSE LLC # # All modifications and additions to the file contributed by third parties # remain the property of their copyright owners, unless otherwise agreed @@ -33,7 +33,8 @@ %bcond_with openmp %endif # LLVM currently doesn't build with Gold on ppc -%ifarch ppc +# Gold is not supported on riscv64 +%ifarch ppc riscv64 %bcond_with gold %else %bcond_without gold @@ -116,6 +117,11 @@ Patch28: gwp-asan-lto.patch # Do not use the deprecated platform.linux_distribution. Patch29: libcxx-tests-linux-distribution.patch +# Backports of RISC-V patches (D65634, D66003, D63497, D69723, D60657) +Patch30: clang-riscv64-rv64gc.diff +Patch31: riscv64-suse-linux.patch +Patch32: llvm-riscv64-fix-cffi.diff +Patch33: D60657-riscv-pcrel_lo.diff BuildRequires: binutils-devel >= 2.21.90 %if %{with gold} BuildRequires: binutils-gold @@ -134,7 +140,6 @@ Requires(post): update-alternatives Requires(postun): update-alternatives BuildRoot: %{_tmppath}/%{name}-%{version}-build -ExcludeArch: riscv64 # llvm does not work on s390 ExcludeArch: s390 BuildRequires: gcc @@ -244,8 +249,8 @@ %package -n clang%{_sonum}-include-fixer Summary: Automatically add missing includes -# Avoid multiple provider errors Group: Development/Languages/C and C++ +# Avoid multiple provider errors Requires: libclang%{_sonum} = %{version} Conflicts: clang-include-fixer < %{version} Conflicts: find-all-symbols < %{version} @@ -266,8 +271,8 @@ %package -n libclang%{_sonum} Summary: Library files needed for clang -# Avoid multiple provider errors Group: System/Libraries +# Avoid multiple provider errors Requires: libLLVM%{_sonum} %description -n libclang%{_sonum} @@ -301,8 +306,8 @@ %package -n libLTO%{_sonum} Summary: Link-time optimizer for LLVM -# Avoid multiple provider errors Group: System/Libraries +# Avoid multiple provider errors Requires: libLLVM%{_sonum} %description -n libLTO%{_sonum} @@ -310,8 +315,8 @@ %package LTO-devel Summary: Link-time optimizer for LLVM (devel package) -# Avoid multiple provider errors Group: Development/Libraries/C and C++ +# Avoid multiple provider errors Requires: %{name}-devel = %{version} Requires: libLTO%{_sonum} Conflicts: libLTO.so < %{version} @@ -323,8 +328,8 @@ %package gold Summary: Gold linker plugin for LLVM -# Avoid multiple provider errors Group: Development/Tools/Building +# Avoid multiple provider errors Requires: libLLVM%{_sonum} Conflicts: llvm-gold-provider < %{version} Provides: llvm-gold-provider = %{version} @@ -334,8 +339,8 @@ %package -n libomp%{_sonum}-devel Summary: MPI plugin for LLVM -# Avoid multiple provider errors Group: Development/Libraries/C and C++ +# Avoid multiple provider errors Requires: libLLVM%{_sonum} Conflicts: libomp-devel < %{version} Provides: libomp-devel = %{version} @@ -356,8 +361,8 @@ %package -n libc++-devel Summary: C++ standard library implementation (devel package) -# Avoid multiple provider errors Group: Development/Libraries/C and C++ +# Avoid multiple provider errors Requires: libc++%{_socxx} = %{version} Requires: libc++abi-devel = %{version} Conflicts: libc++.so < %{version} @@ -475,8 +480,8 @@ %package -n liblldb%{_sonum} Summary: LLDB software debugger runtime library -# Avoid multiple provider errors Group: System/Libraries +# Avoid multiple provider errors Requires: libLLVM%{_sonum} Requires: libclang%{_sonum} @@ -485,8 +490,8 @@ %package -n lldb%{_sonum}-devel Summary: Development files for LLDB -# Avoid multiple provider errors Group: Development/Libraries/C and C++ +# Avoid multiple provider errors Requires: clang%{_sonum}-devel = %{version} Requires: liblldb%{_sonum} = %{version} Requires: llvm%{_sonum}-devel = %{version} @@ -553,6 +558,8 @@ %patch21 -p1 %patch22 -p1 %patch24 -p1 +%patch32 -p1 +%patch33 -p1 pushd compiler-rt-%{version}.src %patch28 -p2 @@ -566,6 +573,8 @@ %patch8 -p1 %patch9 -p2 %patch26 -p1 +%patch30 -p1 +%patch31 -p1 # We hardcode openSUSE rm unittests/Driver/DistroTest.cpp @@ -1673,8 +1682,10 @@ # The sanitizer runtime is not available for ppc. %ifnarch ppc %{_libdir}/clang/%{_relver}/lib +%ifnarch riscv64 %{_libdir}/clang/%{_relver}/share %endif +%endif %{_datadir}/bash-completion/completions/clang.sh %files -n clang%{_sonum}-checker ++++++ D60657-riscv-pcrel_lo.diff ++++++ commit 41449c58c58e466bcf9cdc4f7415950382bad8d7 Author: Roger Ferrer Ibanez <[email protected]> Date: Fri Nov 8 08:26:30 2019 +0000 [RISCV] Fix evaluation of %pcrel_lo The following testcase function: .Lpcrel_label1: auipc a0, %pcrel_hi(other_function) addi a1, a0, %pcrel_lo(.Lpcrel_label1) .p2align 2 # Causes a new fragment to be emitted .type other_function,@function other_function: ret exposes an odd behaviour in which only the %pcrel_hi relocation is evaluated but not the %pcrel_lo. $ llvm-mc -triple riscv64 -filetype obj t.s | llvm-objdump -d -r - <stdin>: file format ELF64-riscv Disassembly of section .text: 0000000000000000 function: 0: 17 05 00 00 auipc a0, 0 4: 93 05 05 00 mv a1, a0 0000000000000004: R_RISCV_PCREL_LO12_I other_function+4 0000000000000008 other_function: 8: 67 80 00 00 ret The reason seems to be that in RISCVAsmBackend::shouldForceRelocation we only consider the fragment but in RISCVMCExpr::evaluatePCRelLo we consider the section. This usually works but there are cases where the section may still be the same but the fragment may be another one. In that case we end forcing a %pcrel_lo relocation without any %pcrel_hi. This patch makes RISCVAsmBackend::shouldForceRelocation use the section, if any, to determine if the relocation must be forced or not. Differential Revision: https://reviews.llvm.org/D60657 Index: llvm-9.0.1.src/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp =================================================================== --- llvm-9.0.1.src.orig/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp +++ llvm-9.0.1.src/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp @@ -57,11 +57,15 @@ bool RISCVAsmBackend::shouldForceRelocat case RISCV::fixup_riscv_tls_gd_hi20: ShouldForce = true; break; - case RISCV::fixup_riscv_pcrel_hi20: - ShouldForce = T->getValue()->findAssociatedFragment() != - Fixup.getValue()->findAssociatedFragment(); + case RISCV::fixup_riscv_pcrel_hi20: { + MCFragment *TFragment = T->getValue()->findAssociatedFragment(); + MCFragment *FixupFragment = Fixup.getValue()->findAssociatedFragment(); + assert(FixupFragment && "We should have a fragment for this fixup"); + ShouldForce = + !TFragment || TFragment->getParent() != FixupFragment->getParent(); break; } + } break; } ++++++ _constraints ++++++ --- /var/tmp/diff_new_pack.Q6xWzO/_old 2020-01-06 16:01:53.161716381 +0100 +++ /var/tmp/diff_new_pack.Q6xWzO/_new 2020-01-06 16:01:53.161716381 +0100 @@ -51,4 +51,17 @@ </memory> </hardware> </overwrite> + <overwrite> + <conditions> + <arch>riscv64</arch> + </conditions> + <hardware> + <disk> + <size unit="G">55</size> + </disk> + <memory> + <size unit="M">14000</size> + </memory> + </hardware> + </overwrite> </constraints> ++++++ clang-riscv64-rv64gc.diff ++++++ commit 93c4d53b0a5 Author: Roger Ferrer Ibanez <[email protected]> Date: Tue Sep 10 08:16:24 2019 +0000 [RISCV] Make -march=rv{32,64}gc the default in RISC-V Linux This is the logical follow-up of D65634. Differential Revision: https://reviews.llvm.org/D66003 llvm-svn: 371496 Index: clang-9.0.1.src/lib/Driver/ToolChains/Arch/RISCV.cpp =================================================================== --- clang-9.0.1.src.orig/lib/Driver/ToolChains/Arch/RISCV.cpp +++ clang-9.0.1.src/lib/Driver/ToolChains/Arch/RISCV.cpp @@ -12,6 +12,7 @@ #include "clang/Driver/DriverDiagnostic.h" #include "clang/Driver/Options.h" #include "llvm/Option/ArgList.h" +#include "llvm/ADT/Optional.h" #include "llvm/Support/TargetParser.h" #include "llvm/Support/raw_ostream.h" #include "ToolChains/CommonArgs.h" @@ -189,168 +190,182 @@ static void getExtensionFeatures(const D } } -void riscv::getRISCVTargetFeatures(const Driver &D, const ArgList &Args, - std::vector<StringRef> &Features) { - if (const Arg *A = Args.getLastArg(options::OPT_march_EQ)) { - StringRef MArch = A->getValue(); +// Returns false if an error is diagnosed. +static bool getArchFeatures(const Driver &D, StringRef MArch, + std::vector<StringRef> &Features, + const ArgList &Args) { + // RISC-V ISA strings must be lowercase. + if (llvm::any_of(MArch, [](char c) { return isupper(c); })) { + D.Diag(diag::err_drv_invalid_riscv_arch_name) + << MArch << "string must be lowercase"; + return false; + } - // RISC-V ISA strings must be lowercase. - if (llvm::any_of(MArch, [](char c) { return isupper(c); })) { - D.Diag(diag::err_drv_invalid_riscv_arch_name) - << MArch << "string must be lowercase"; - return; - } + // ISA string must begin with rv32 or rv64. + if (!(MArch.startswith("rv32") || MArch.startswith("rv64")) || + (MArch.size() < 5)) { + D.Diag(diag::err_drv_invalid_riscv_arch_name) + << MArch << "string must begin with rv32{i,e,g} or rv64{i,g}"; + return false; + } - // ISA string must begin with rv32 or rv64. - if (!(MArch.startswith("rv32") || MArch.startswith("rv64")) || - (MArch.size() < 5)) { - D.Diag(diag::err_drv_invalid_riscv_arch_name) << MArch - << "string must begin with rv32{i,e,g} or rv64{i,g}"; - return; - } + bool HasRV64 = MArch.startswith("rv64"); - bool HasRV64 = MArch.startswith("rv64"); + // The canonical order specified in ISA manual. + // Ref: Table 22.1 in RISC-V User-Level ISA V2.2 + StringRef StdExts = "mafdqlcbjtpvn"; + bool HasF = false, HasD = false; + char Baseline = MArch[4]; + + // First letter should be 'e', 'i' or 'g'. + switch (Baseline) { + default: + D.Diag(diag::err_drv_invalid_riscv_arch_name) + << MArch << "first letter should be 'e', 'i' or 'g'"; + return false; + case 'e': { + StringRef Error; + // Currently LLVM does not support 'e'. + // Extension 'e' is not allowed in rv64. + if (HasRV64) + Error = "standard user-level extension 'e' requires 'rv32'"; + else + Error = "unsupported standard user-level extension 'e'"; + D.Diag(diag::err_drv_invalid_riscv_arch_name) << MArch << Error; + return false; + } + case 'i': + break; + case 'g': + // g = imafd + StdExts = StdExts.drop_front(4); + Features.push_back("+m"); + Features.push_back("+a"); + Features.push_back("+f"); + Features.push_back("+d"); + HasF = true; + HasD = true; + break; + } - // The canonical order specified in ISA manual. - // Ref: Table 22.1 in RISC-V User-Level ISA V2.2 - StringRef StdExts = "mafdqlcbjtpvn"; - bool HasF = false, HasD = false; - char Baseline = MArch[4]; + // Skip rvxxx + StringRef Exts = MArch.substr(5); - // First letter should be 'e', 'i' or 'g'. - switch (Baseline) { - default: - D.Diag(diag::err_drv_invalid_riscv_arch_name) << MArch - << "first letter should be 'e', 'i' or 'g'"; - return; - case 'e': { + // Remove non-standard extensions and supervisor-level extensions. + // They have 'x', 's', 'sx' prefixes. Parse them at the end. + // Find the very first occurrence of 's' or 'x'. + StringRef OtherExts; + size_t Pos = Exts.find_first_of("sx"); + if (Pos != StringRef::npos) { + OtherExts = Exts.substr(Pos); + Exts = Exts.substr(0, Pos); + } + + std::string Major, Minor; + if (!getExtensionVersion(D, MArch, std::string(1, Baseline), Exts, Major, + Minor)) + return false; + + // TODO: Use version number when setting target features + // and consume the underscore '_' that might follow. + + auto StdExtsItr = StdExts.begin(); + auto StdExtsEnd = StdExts.end(); + + for (auto I = Exts.begin(), E = Exts.end(); I != E; ++I) { + char c = *I; + + // Check ISA extensions are specified in the canonical order. + while (StdExtsItr != StdExtsEnd && *StdExtsItr != c) + ++StdExtsItr; + + if (StdExtsItr == StdExtsEnd) { + // Either c contains a valid extension but it was not given in + // canonical order or it is an invalid extension. StringRef Error; - // Currently LLVM does not support 'e'. - // Extension 'e' is not allowed in rv64. - if (HasRV64) - Error = "standard user-level extension 'e' requires 'rv32'"; + if (StdExts.contains(c)) + Error = "standard user-level extension not given in canonical order"; else - Error = "unsupported standard user-level extension 'e'"; - D.Diag(diag::err_drv_invalid_riscv_arch_name) - << MArch << Error; - return; + Error = "invalid standard user-level extension"; + D.Diag(diag::err_drv_invalid_riscv_ext_arch_name) + << MArch << Error << std::string(1, c); + return false; } - case 'i': - break; - case 'g': - // g = imafd - StdExts = StdExts.drop_front(4); + + // Move to next char to prevent repeated letter. + ++StdExtsItr; + + if (std::next(I) != E) { + // Skip c. + std::string Next = std::string(std::next(I), E); + std::string Major, Minor; + if (!getExtensionVersion(D, MArch, std::string(1, c), Next, Major, Minor)) + return false; + + // TODO: Use version number when setting target features + // and consume the underscore '_' that might follow. + } + + // The order is OK, then push it into features. + switch (c) { + default: + // Currently LLVM supports only "mafdc". + D.Diag(diag::err_drv_invalid_riscv_ext_arch_name) + << MArch << "unsupported standard user-level extension" + << std::string(1, c); + return false; + case 'm': Features.push_back("+m"); + break; + case 'a': Features.push_back("+a"); + break; + case 'f': Features.push_back("+f"); - Features.push_back("+d"); HasF = true; + break; + case 'd': + Features.push_back("+d"); HasD = true; break; + case 'c': + Features.push_back("+c"); + break; } + } - // Skip rvxxx - StringRef Exts = MArch.substr(5); - - // Remove non-standard extensions and supervisor-level extensions. - // They have 'x', 's', 'sx' prefixes. Parse them at the end. - // Find the very first occurrence of 's' or 'x'. - StringRef OtherExts; - size_t Pos = Exts.find_first_of("sx"); - if (Pos != StringRef::npos) { - OtherExts = Exts.substr(Pos); - Exts = Exts.substr(0, Pos); - } - - std::string Major, Minor; - if (!getExtensionVersion(D, MArch, std::string(1, Baseline), - Exts, Major, Minor)) - return; - - // TODO: Use version number when setting target features - // and consume the underscore '_' that might follow. - - auto StdExtsItr = StdExts.begin(); - auto StdExtsEnd = StdExts.end(); - - for (auto I = Exts.begin(), E = Exts.end(); I != E; ++I) { - char c = *I; + // Dependency check. + // It's illegal to specify the 'd' (double-precision floating point) + // extension without also specifying the 'f' (single precision + // floating-point) extension. + if (HasD && !HasF) { + D.Diag(diag::err_drv_invalid_riscv_arch_name) + << MArch << "d requires f extension to also be specified"; + return false; + } - // Check ISA extensions are specified in the canonical order. - while (StdExtsItr != StdExtsEnd && *StdExtsItr != c) - ++StdExtsItr; - - if (StdExtsItr == StdExtsEnd) { - // Either c contains a valid extension but it was not given in - // canonical order or it is an invalid extension. - StringRef Error; - if (StdExts.contains(c)) - Error = "standard user-level extension not given in canonical order"; - else - Error = "invalid standard user-level extension"; - D.Diag(diag::err_drv_invalid_riscv_ext_arch_name) - << MArch << Error << std::string(1, c); - return; - } + // Additional dependency checks. + // TODO: The 'q' extension requires rv64. + // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'. - // Move to next char to prevent repeated letter. - ++StdExtsItr; + // Handle all other types of extensions. + getExtensionFeatures(D, Args, Features, MArch, OtherExts); - if (std::next(I) != E) { - // Skip c. - std::string Next = std::string(std::next(I), E); - std::string Major, Minor; - if (!getExtensionVersion(D, MArch, std::string(1, c), - Next, Major, Minor)) - return; - - // TODO: Use version number when setting target features - // and consume the underscore '_' that might follow. - } - - // The order is OK, then push it into features. - switch (c) { - default: - // Currently LLVM supports only "mafdc". - D.Diag(diag::err_drv_invalid_riscv_ext_arch_name) - << MArch << "unsupported standard user-level extension" - << std::string(1, c); - return; - case 'm': - Features.push_back("+m"); - break; - case 'a': - Features.push_back("+a"); - break; - case 'f': - Features.push_back("+f"); - HasF = true; - break; - case 'd': - Features.push_back("+d"); - HasD = true; - break; - case 'c': - Features.push_back("+c"); - break; - } - } - - // Dependency check. - // It's illegal to specify the 'd' (double-precision floating point) - // extension without also specifying the 'f' (single precision - // floating-point) extension. - if (HasD && !HasF) - D.Diag(diag::err_drv_invalid_riscv_arch_name) << MArch - << "d requires f extension to also be specified"; + return true; +} - // Additional dependency checks. - // TODO: The 'q' extension requires rv64. - // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'. +void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple, + const ArgList &Args, + std::vector<StringRef> &Features) { + llvm::Optional<StringRef> MArch; + if (const Arg *A = Args.getLastArg(options::OPT_march_EQ)) + MArch = A->getValue(); + else if (Triple.getOS() == llvm::Triple::Linux) + // RISC-V Linux defaults to rv{32,64}gc. + MArch = Triple.getArch() == llvm::Triple::riscv32 ? "rv32gc" : "rv64gc"; - // Handle all other types of extensions. - getExtensionFeatures(D, Args, Features, MArch, OtherExts); - } + if (MArch.hasValue() && !getArchFeatures(D, *MArch, Features, Args)) + return; // -mrelax is default, unless -mno-relax is specified. if (Args.hasFlag(options::OPT_mrelax, options::OPT_mno_relax, true)) @@ -372,8 +387,16 @@ void riscv::getRISCVTargetFeatures(const } StringRef riscv::getRISCVABI(const ArgList &Args, const llvm::Triple &Triple) { - if (Arg *A = Args.getLastArg(options::OPT_mabi_EQ)) + assert((Triple.getArch() == llvm::Triple::riscv32 || + Triple.getArch() == llvm::Triple::riscv64) && + "Unexpected triple"); + + if (const Arg *A = Args.getLastArg(options::OPT_mabi_EQ)) return A->getValue(); - return Triple.getArch() == llvm::Triple::riscv32 ? "ilp32" : "lp64"; + // RISC-V Linux defaults to ilp32d/lp64d + if (Triple.getOS() == llvm::Triple::Linux) + return Triple.getArch() == llvm::Triple::riscv32 ? "ilp32d" : "lp64d"; + else + return Triple.getArch() == llvm::Triple::riscv32 ? "ilp32" : "lp64"; } Index: clang-9.0.1.src/lib/Driver/ToolChains/Arch/RISCV.h =================================================================== --- clang-9.0.1.src.orig/lib/Driver/ToolChains/Arch/RISCV.h +++ clang-9.0.1.src/lib/Driver/ToolChains/Arch/RISCV.h @@ -19,7 +19,8 @@ namespace clang { namespace driver { namespace tools { namespace riscv { -void getRISCVTargetFeatures(const Driver &D, const llvm::opt::ArgList &Args, +void getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple, + const llvm::opt::ArgList &Args, std::vector<llvm::StringRef> &Features); StringRef getRISCVABI(const llvm::opt::ArgList &Args, const llvm::Triple &Triple); Index: clang-9.0.1.src/lib/Driver/ToolChains/Clang.cpp =================================================================== --- clang-9.0.1.src.orig/lib/Driver/ToolChains/Clang.cpp +++ clang-9.0.1.src/lib/Driver/ToolChains/Clang.cpp @@ -335,7 +335,7 @@ static void getTargetFeatures(const Tool break; case llvm::Triple::riscv32: case llvm::Triple::riscv64: - riscv::getRISCVTargetFeatures(D, Args, Features); + riscv::getRISCVTargetFeatures(D, Triple, Args, Features); break; case llvm::Triple::systemz: systemz::getSystemZTargetFeatures(Args, Features); @@ -1853,21 +1853,11 @@ void Clang::AddPPCTargetArgs(const ArgLi void Clang::AddRISCVTargetArgs(const ArgList &Args, ArgStringList &CmdArgs) const { - // FIXME: currently defaults to the soft-float ABIs. Will need to be - // expanded to select ilp32f, ilp32d, lp64f, lp64d when appropriate. - const char *ABIName = nullptr; const llvm::Triple &Triple = getToolChain().getTriple(); - if (Arg *A = Args.getLastArg(options::OPT_mabi_EQ)) - ABIName = A->getValue(); - else if (Triple.getArch() == llvm::Triple::riscv32) - ABIName = "ilp32"; - else if (Triple.getArch() == llvm::Triple::riscv64) - ABIName = "lp64"; - else - llvm_unreachable("Unexpected triple!"); + StringRef ABIName = riscv::getRISCVABI(Args, Triple); CmdArgs.push_back("-target-abi"); - CmdArgs.push_back(ABIName); + CmdArgs.push_back(ABIName.data()); } void Clang::AddSparcTargetArgs(const ArgList &Args, Index: clang-9.0.1.src/test/Driver/riscv32-toolchain.c =================================================================== --- clang-9.0.1.src.orig/test/Driver/riscv32-toolchain.c +++ clang-9.0.1.src/test/Driver/riscv32-toolchain.c @@ -68,7 +68,7 @@ // CXX-RV32-BAREMETAL-NOSYSROOT-ILP32: "{{.*}}/Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1{{/|\\\\}}crtend.o" // RUN: %clang %s -### -no-canonical-prefixes -fuse-ld=ld \ -// RUN: -target riscv32-unknown-linux-gnu \ +// RUN: -target riscv32-unknown-linux-gnu -mabi=ilp32 \ // RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_linux_sdk \ // RUN: --sysroot=%S/Inputs/multilib_riscv_linux_sdk/sysroot 2>&1 \ // RUN: | FileCheck -check-prefix=C-RV32-LINUX-MULTI-ILP32 %s @@ -84,7 +84,7 @@ // C-RV32-LINUX-MULTI-ILP32: "-L{{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot/usr/lib32/ilp32" // RUN: %clang %s -### -no-canonical-prefixes -fuse-ld=ld \ -// RUN: -target riscv32-unknown-linux-gnu -march=rv32imafd -mabi=ilp32d \ +// RUN: -target riscv32-unknown-linux-gnu -march=rv32imafd \ // RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_linux_sdk \ // RUN: --sysroot=%S/Inputs/multilib_riscv_linux_sdk/sysroot 2>&1 \ // RUN: | FileCheck -check-prefix=C-RV32-LINUX-MULTI-ILP32D %s Index: clang-9.0.1.src/test/Driver/riscv64-toolchain.c =================================================================== --- clang-9.0.1.src.orig/test/Driver/riscv64-toolchain.c +++ clang-9.0.1.src/test/Driver/riscv64-toolchain.c @@ -68,7 +68,7 @@ // CXX-RV64-BAREMETAL-NOSYSROOT-LP64: "{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|\\\\}}crtend.o" // RUN: %clang %s -### -no-canonical-prefixes -fuse-ld=ld \ -// RUN: -target riscv64-unknown-linux-gnu \ +// RUN: -target riscv64-unknown-linux-gnu -mabi=lp64 \ // RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_linux_sdk \ // RUN: --sysroot=%S/Inputs/multilib_riscv_linux_sdk/sysroot 2>&1 \ // RUN: | FileCheck -check-prefix=C-RV64-LINUX-MULTI-LP64 %s @@ -84,7 +84,7 @@ // C-RV64-LINUX-MULTI-LP64: "-L{{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot/usr/lib64/lp64" // RUN: %clang %s -### -no-canonical-prefixes -fuse-ld=ld \ -// RUN: -target riscv64-unknown-linux-gnu -march=rv64imafd -mabi=lp64d \ +// RUN: -target riscv64-unknown-linux-gnu -march=rv64imafd \ // RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_linux_sdk \ // RUN: --sysroot=%S/Inputs/multilib_riscv_linux_sdk/sysroot 2>&1 \ // RUN: | FileCheck -check-prefix=C-RV64-LINUX-MULTI-LP64D %s Index: clang-9.0.1.src/test/Preprocessor/riscv-target-features.c =================================================================== --- clang-9.0.1.src.orig/test/Preprocessor/riscv-target-features.c +++ clang-9.0.1.src/test/Preprocessor/riscv-target-features.c @@ -48,9 +48,9 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s // CHECK-C-EXT: __riscv_compressed 1 -// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ifd -x c -E -dM %s \ +// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ifd -mabi=ilp32 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-SOFT %s -// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ifd -x c -E -dM %s \ +// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ifd -mabi=lp64 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-SOFT %s // CHECK-SOFT: __riscv_float_abi_soft 1 // CHECK-SOFT-NOT: __riscv_float_abi_single @@ -64,9 +64,9 @@ // CHECK-SINGLE-NOT: __riscv_float_abi_soft // CHECK-SINGLE-NOT: __riscv_float_abi_double -// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ifd -mabi=ilp32d -x c -E -dM %s \ +// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ifd -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-DOUBLE %s -// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ifd -mabi=lp64d -x c -E -dM %s \ +// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ifd -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-DOUBLE %s // CHECK-DOUBLE: __riscv_float_abi_double 1 // CHECK-DOUBLE-NOT: __riscv_float_abi_soft ++++++ llvm-riscv64-fix-cffi.diff ++++++ commit c6b09bff5671600f8e764d3847023d0996f328d9 Author: Luís Marques <[email protected]> Date: Thu Nov 14 18:27:42 2019 +0000 [RISCV] Fix wrong CFI directives Summary: Removes CFI CFA directives that could incorrectly propagate beyond the basic block they were inteded for. Specifically it removes the epilogue CFI directives. See the branch_and_tail_call test for an example of the issue. Should fix the stack unwinding issues caused by the incorrect directives. Reviewers: asb, lenary, shiva0217 Reviewed By: lenary Tags: #llvm Differential Revision: https://reviews.llvm.org/D69723 Index: llvm-9.0.1.src/lib/Target/RISCV/RISCVFrameLowering.cpp =================================================================== --- llvm-9.0.1.src.orig/lib/Target/RISCV/RISCVFrameLowering.cpp +++ llvm-9.0.1.src/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -205,7 +205,6 @@ void RISCVFrameLowering::emitEpilogue(Ma MachineFrameInfo &MFI = MF.getFrameInfo(); auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>(); DebugLoc DL = MBBI->getDebugLoc(); - const RISCVInstrInfo *TII = STI.getInstrInfo(); unsigned FPReg = getFPReg(STI); unsigned SPReg = getSPReg(STI); @@ -226,47 +225,8 @@ void RISCVFrameLowering::emitEpilogue(Ma MachineInstr::FrameDestroy); } - if (hasFP(MF)) { - // To find the instruction restoring FP from stack. - for (auto &I = LastFrameDestroy; I != MBBI; ++I) { - if (I->mayLoad() && I->getOperand(0).isReg()) { - unsigned DestReg = I->getOperand(0).getReg(); - if (DestReg == FPReg) { - // If there is frame pointer, after restoring $fp registers, we - // need adjust CFA to ($sp - FPOffset). - // Emit ".cfi_def_cfa $sp, -FPOffset" - unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa( - nullptr, RI->getDwarfRegNum(SPReg, true), -FPOffset)); - BuildMI(MBB, std::next(I), DL, - TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex); - break; - } - } - } - } - - // Add CFI directives for callee-saved registers. - const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo(); - // Iterate over list of callee-saved registers and emit .cfi_restore - // directives. - for (const auto &Entry : CSI) { - unsigned Reg = Entry.getReg(); - unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore( - nullptr, RI->getDwarfRegNum(Reg, true))); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex); - } - // Deallocate stack adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackSize, MachineInstr::FrameDestroy); - - // After restoring $sp, we need to adjust CFA to $(sp + 0) - // Emit ".cfi_def_cfa_offset 0" - unsigned CFIIndex = - MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex); } int RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, Index: llvm-9.0.1.src/test/CodeGen/RISCV/exception-pointer-register.ll =================================================================== --- llvm-9.0.1.src.orig/test/CodeGen/RISCV/exception-pointer-register.ll +++ llvm-9.0.1.src/test/CodeGen/RISCV/exception-pointer-register.ll @@ -40,11 +40,7 @@ define void @caller(i1* %p) personality ; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw ra, 12(sp) -; RV32I-NEXT: .cfi_restore ra -; RV32I-NEXT: .cfi_restore s0 -; RV32I-NEXT: .cfi_restore s1 ; RV32I-NEXT: addi sp, sp, 16 -; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; RV32I-NEXT: .LBB0_4: # %lpad ; RV32I-NEXT: .Ltmp4: @@ -81,11 +77,7 @@ define void @caller(i1* %p) personality ; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld ra, 24(sp) -; RV64I-NEXT: .cfi_restore ra -; RV64I-NEXT: .cfi_restore s0 -; RV64I-NEXT: .cfi_restore s1 ; RV64I-NEXT: addi sp, sp, 32 -; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; RV64I-NEXT: .LBB0_4: # %lpad ; RV64I-NEXT: .Ltmp4: @@ -119,12 +111,10 @@ end2: define internal void @callee(i1* %p) { ; RV32I-LABEL: callee: ; RV32I: # %bb.0: -; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV64I-LABEL: callee: ; RV64I: # %bb.0: -; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ret void } Index: llvm-9.0.1.src/test/CodeGen/RISCV/frame-info.ll =================================================================== --- llvm-9.0.1.src.orig/test/CodeGen/RISCV/frame-info.ll +++ llvm-9.0.1.src/test/CodeGen/RISCV/frame-info.ll @@ -20,12 +20,8 @@ define void @foo(i32 signext %size) { ; RV32-NEXT: call bar ; RV32-NEXT: addi sp, s0, -16 ; RV32-NEXT: lw s0, 8(sp) -; RV32-NEXT: .cfi_def_cfa sp, 16 ; RV32-NEXT: lw ra, 12(sp) -; RV32-NEXT: .cfi_restore ra -; RV32-NEXT: .cfi_restore s0 ; RV32-NEXT: addi sp, sp, 16 -; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: foo: @@ -50,12 +46,8 @@ define void @foo(i32 signext %size) { ; RV64-NEXT: call bar ; RV64-NEXT: addi sp, s0, -16 ; RV64-NEXT: ld s0, 0(sp) -; RV64-NEXT: .cfi_def_cfa sp, 16 ; RV64-NEXT: ld ra, 8(sp) -; RV64-NEXT: .cfi_restore ra -; RV64-NEXT: .cfi_restore s0 ; RV64-NEXT: addi sp, sp, 16 -; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret entry: %0 = alloca i8, i32 %size, align 16 Index: llvm-9.0.1.src/test/CodeGen/RISCV/split-offsets.ll =================================================================== --- llvm-9.0.1.src.orig/test/CodeGen/RISCV/split-offsets.ll +++ llvm-9.0.1.src/test/CodeGen/RISCV/split-offsets.ll @@ -22,7 +22,6 @@ define void @test1([65536 x i32]** %sp, ; RV32I-NEXT: add a0, a1, a2 ; RV32I-NEXT: sw a4, 4(a0) ; RV32I-NEXT: sw a3, 0(a0) -; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV64I-LABEL: test1: @@ -38,7 +37,6 @@ define void @test1([65536 x i32]** %sp, ; RV64I-NEXT: add a0, a1, a2 ; RV64I-NEXT: sw a4, 4(a0) ; RV64I-NEXT: sw a3, 0(a0) -; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret entry: %s = load [65536 x i32]*, [65536 x i32]** %sp @@ -74,7 +72,6 @@ define void @test2([65536 x i32]** %sp, ; RV32I-NEXT: mv a3, a4 ; RV32I-NEXT: blt a3, a2, .LBB1_1 ; RV32I-NEXT: .LBB1_2: # %while_end -; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV64I-LABEL: test2: @@ -99,7 +96,6 @@ define void @test2([65536 x i32]** %sp, ; RV64I-NEXT: sext.w a4, a3 ; RV64I-NEXT: blt a4, a2, .LBB1_1 ; RV64I-NEXT: .LBB1_2: # %while_end -; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret entry: %s = load [65536 x i32]*, [65536 x i32]** %sp ++++++ riscv64-suse-linux.patch ++++++ commit 1fc2a47f0b6 Author: Sam Elliott <[email protected]> Date: Thu Aug 1 14:23:56 2019 +0000 Add support for openSUSE RISC-V triple Reviewers: asb Reviewed By: asb Subscribers: lenary, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, lebedev.ri, kito-cheng, shiva0217, rogfer01, dexonsmith, rkruppe, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D63497 Patch by Andreas Schwab (schwab) llvm-svn: 367565 Index: clang-9.0.1.src/lib/Driver/ToolChains/Gnu.cpp =================================================================== --- clang-9.0.1.src.orig/lib/Driver/ToolChains/Gnu.cpp +++ clang-9.0.1.src/lib/Driver/ToolChains/Gnu.cpp @@ -2018,7 +2018,8 @@ void Generic_GCC::GCCInstallationDetecto static const char *const RISCV64LibDirs[] = {"/lib64", "/lib"}; static const char *const RISCV64Triples[] = {"riscv64-unknown-linux-gnu", "riscv64-linux-gnu", - "riscv64-unknown-elf"}; + "riscv64-unknown-elf", + "riscv64-suse-linux"}; static const char *const SPARCv8LibDirs[] = {"/lib32", "/lib"}; static const char *const SPARCv8Triples[] = {"sparc-linux-gnu",
