Hello community, here is the log from the commit of package cpuid for openSUSE:Factory checked in at 2020-04-29 20:51:23 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/cpuid (Old) and /work/SRC/openSUSE:Factory/.cpuid.new.2738 (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "cpuid" Wed Apr 29 20:51:23 2020 rev:10 rq:798738 version:20200427 Changes: -------- --- /work/SRC/openSUSE:Factory/cpuid/cpuid.changes 2020-03-09 11:43:01.969345150 +0100 +++ /work/SRC/openSUSE:Factory/.cpuid.new.2738/cpuid.changes 2020-04-29 20:53:23.169135833 +0200 @@ -1,0 +2,20 @@ +Tue Apr 28 18:54:25 UTC 2020 - Andreas Stieger <andreas.stie...@gmx.de> + +- update to 20200427: + * Add synth decoding for AMD Steppe Eagle/Crowned Eagle + (Puma 2014 G-Series), based on instlatx64 sample + * Add 7/0/edx SERIALIZE & TSXLDTRK bit descriptions + * Add 0xf/1/eax Counter width & overflow flag + * Add 0x10/3/ecx per-thread MBA controls flag + * Add 0x8000001f fields + * Add AMD 24594 & 40332 docs + * Correct field lengths in 14/0 and 14/1 subleafs so that + columns line up + * Add CC150 (Coffee Lake R0) synth decoding, based on + instlatx64 example + * Add Jasper Lake A0 stepping (from Coreboot*) + * Update 1/ebx "cpu count" to modern terminology: "maximum + addressible IDs for CPUs in pkg" to avoid user confusion + * Update 4/eax CPU & core count terminology in the same way + +------------------------------------------------------------------- Old: ---- cpuid-20200211.src.tar.gz New: ---- cpuid-20200427.src.tar.gz ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ cpuid.spec ++++++ --- /var/tmp/diff_new_pack.t2TeOQ/_old 2020-04-29 20:53:24.397138646 +0200 +++ /var/tmp/diff_new_pack.t2TeOQ/_new 2020-04-29 20:53:24.401138655 +0200 @@ -17,13 +17,12 @@ Name: cpuid -Version: 20200211 +Version: 20200427 Release: 0 Summary: x86 CPU identification tool License: GPL-2.0-or-later Group: System/Management URL: http://etallen.com/cpuid.html - Source: http://etallen.com/cpuid/%name-%version.src.tar.gz BuildRequires: gcc BuildRequires: glibc-devel @@ -42,7 +41,7 @@ # remove -Werror=format-security which is used on Mandriva, as it produces # a false positive compiler error on several printf calls: CFLAGS=$(echo "%optflags -Wall" | sed 's/-Werror=format-security//g') -make CFLAGS="$CFLAGS" +%make_build CFLAGS="$CFLAGS" %install mkdir -p "%buildroot/%_bindir" "%buildroot/%_mandir/man1" ++++++ cpuid-20200211.src.tar.gz -> cpuid-20200427.src.tar.gz ++++++ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20200211/ChangeLog new/cpuid-20200427/ChangeLog --- old/cpuid-20200211/ChangeLog 2020-02-11 10:35:22.000000000 +0100 +++ new/cpuid-20200427/ChangeLog 2020-04-27 14:10:31.000000000 +0200 @@ -1,3 +1,33 @@ +Mon Apr 27 2020 Todd Allen <todd.al...@etallen.com> + * Made new release. + +Wed Apr 22 2020 Todd Allen <todd.al...@etallen.com> + * cpuid.c: Added synth decoding for AMD Steppe Eagle/Crowned Eagle + (Puma 2014 G-Series), based on instlatx64 sample. + +Thu Apr 16 2020 Todd Allen <todd.al...@etallen.com> + * cpuid.c: Added 7/0/edx SERIALIZE & TSXLDTRK bit descriptions. + * cpuid.c: Added 0xf/1/eax Counter width & overflow flag. + * cpuid.c: Added 0x10/3/ecx per-thread MBA controls flag. + * cpuid.c: Added 0x8000001f fields. + * cpuid.man: Added AMD 24594 & 40332 docs. + +Tue Mar 3 2020 Todd Allen <todd.al...@etallen.com> + * cpuid.c: Corrected field lengths in 14/0 and 14/1 subleafs so that + columns line up. + +Thu Feb 27 2020 Todd Allen <todd.al...@etallen.com> + * cpuid.c: Added CC150 (Coffee Lake R0) synth decoding, based on + instlatx64 example. + +Wed Feb 26 2020 Todd Allen <todd.al...@etallen.com> + * cpuid.c: Added Jasper Lake A0 stepping (from Coreboot*). + * cpuid.c: Updated 1/ebx "cpu count" to modern terminology: "maximum + addressible IDs for CPUs in pkg" to avoid user confusion. It was a + reliable count of the number of CPUs for only a split second some time + around 2002. Maybe. + * cpuid.c: Updated 4/eax CPU & core count terminology in the same way. + Tue Feb 11 2020 Todd Allen <todd.al...@etallen.com> * Made new release. diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20200211/FAMILY.NOTES new/cpuid-20200427/FAMILY.NOTES --- old/cpuid-20200211/FAMILY.NOTES 2020-02-10 14:34:18.000000000 +0100 +++ new/cpuid-20200427/FAMILY.NOTES 2020-04-24 18:23:47.000000000 +0200 @@ -46,7 +46,7 @@ 10000 Series : Sunny Cove : new architecture (Ice Lake) Comet Lake * optim of {Coffee, Whiskey} Lake (K,U) ----------------------------------------------------------------------------- - future : Willow Cove : optim of Sunny Cove (Tiger Lake) + future : Willow Cove : optim of Sunny Cove (Tiger Lake) [summer 2020?] ----------------------------------------------------------------------------- * = I'm not treating this as a distinct uarch, but just as a core within its @@ -154,6 +154,8 @@ ----------------------------------------------------- Silvermont Rangeley ? Rangeley ----------------------------------------------------- + Tremont ? ? Snow Ridge + ----------------------------------------------------- * Canceled core ! Surprising use of wrong-market core @@ -212,12 +214,15 @@ (+) Bristol Ridge/Stoney Ridge Bristol Ridge/Stoney Ridge Prairie Falcon ----------------------------------------------------------------------------------------------------------------------------------- Jaguar Kabini Kabini/Temash Kyoto Kabini - Puma (2014) Beema/Mullins Steppe Eagle/Crowned Eagle + Puma (2014) Beema/Mullins Steppe Eagle (SoC)/Crowned Eagle (CPU) ----------------------------------------------------------------------------------------------------------------------------------- Zen Summit Ridge Raven Ridge Naples/Snowy Owl Great Horned Owl/Banded Kestrel Zen+ Pinnacle Ridge/Picasso/Colfax Picasso Zen 2 Castle Peak Rome (update) Matisse Renoir Dali + ---future-------------------------------------------------------------------------------------------------------------------------- + Zen 3 (7nm) Vermeer Milan [late 2020] + Zen 4 (5nm) Genoa [in 2022] ----------------------------------------------------------------------------------------------------------------------------------- A-Series = APU (Desktop/Mobile) diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20200211/FUTURE new/cpuid-20200427/FUTURE --- old/cpuid-20200211/FUTURE 2020-02-10 13:30:44.000000000 +0100 +++ new/cpuid-20200427/FUTURE 2020-03-06 17:08:11.000000000 +0100 @@ -1,7 +1,9 @@ -Intel: - CC150 CPU seems to be stepping (0,6),(9,14),13 = Coffee Lake R0, brand name - is just "Intel Core". +Gigabyte: + Try using the Gigabyte CPU Support List to verify stepping names. + +-------------------------------------------------------------------------------- +Intel: Cascade Lake refresh Xeons: Xeon Scalable 3xxxR, 4xxxR & 6xxxR (to be released 2020-02-23): still (0,6),(5,5),7? @@ -24,6 +26,7 @@ Atom Elkhart Lake [Tremont] (0,6),(8,6) spec update. (wrong name?) Atom Elkhart Lake [Tremont] (0,6),(9,6) spec update. Atom Jasper Lake [Tremont] (0,6),(9,12) spec update. + Atom P5900 (Snow Ridge?) [Tremont]: f/m/s unknown. Atom [Gracemont] (~2021). Atom Puma 7 (0,6),(6,14) spec update. @@ -44,9 +47,9 @@ Intel: Xeon Phi (Knights Corner) (0,11),(0,1) with 0x20000001 leaf. Intel: Xeon Phi (Knights Mill) (0,6),(8,5). Intel: Atom Z3400 (Merrifield) [Silvermont] (0,6),(4,10). - Intel: Atom (Apollo Lake) (0,6),(5,12),2. - Intel: Atom x3-C3000 (SoFIA) (0,6),(5,13). - Intel: Spreadtrum SC9853I-IA (0,6),(7,5). + Intel: Atom (Apollo Lake) [Goldmont] (0,6),(5,12),2. + Intel: Atom x3-C3000 (SoFIA) [Silvermont] (0,6),(5,13). + Intel: Spreadtrum SC9853I-IA [Airmont] (0,6),(7,5). Intel: Atom S12x9 (Briarwood) is based on Cedar Trail, but the Intel docs provide no CPUID identification values. And I can find no examples online. Does anyone know the CPUID family/model/steppings? diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20200211/Makefile new/cpuid-20200427/Makefile --- old/cpuid-20200211/Makefile 2020-02-11 10:35:08.000000000 +0100 +++ new/cpuid-20200427/Makefile 2020-04-27 14:09:46.000000000 +0200 @@ -8,7 +8,7 @@ INSTALL_STRIP=-s PACKAGE=cpuid -VERSION=20200211 +VERSION=20200427 RELEASE=1 PROG=$(PACKAGE) diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20200211/cpuid.c new/cpuid-20200427/cpuid.c --- old/cpuid-20200211/cpuid.c 2020-02-11 00:03:10.000000000 +0100 +++ new/cpuid-20200427/cpuid.c 2020-04-22 14:57:11.000000000 +0200 @@ -378,6 +378,7 @@ boolean g_line; boolean i_8000; boolean i_10000; + boolean cc150; }; struct /* AMD */ { boolean athlon_lv; @@ -467,7 +468,7 @@ { FALSE, \ { FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, \ FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, \ - FALSE, FALSE }, \ + FALSE, FALSE, FALSE }, \ { FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, \ FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, \ FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, \ @@ -1549,6 +1550,7 @@ stash->br.g_line = strregexp(brand, "Core.* [im][3579]-[0-9]*G"); stash->br.i_8000 = strregexp(brand, "Core.* [im][3579]-8[0-9][0-9][0-9]"); stash->br.i_10000 = strregexp(brand, "Core.* i[3579]-10[0-9][0-9][0-9]"); + stash->br.cc150 = strregexp(brand, "CC150"); stash->br.athlon_lv = strstr(brand, "Athlon(tm) XP-M (LV)") != NULL; stash->br.athlon_xp = (strstr(brand, "Athlon(tm) XP") != NULL @@ -1679,6 +1681,7 @@ #define UP (dP && stash->br.u_line) #define YC (dC && stash->br.y_line) #define YP (dP && stash->br.y_line) +#define d1 (is_intel && stash->br.cc150) /* ** Intel special cases @@ -3311,7 +3314,9 @@ // LX*. Coreboot* provides stepping. FMS ( 0, 6, 9, 6, 0, "Intel Atom (Elkhart Lake A0)"); FM ( 0, 6, 9, 6, "Intel Atom (Elkhart Lake)"); - FM ( 0, 6, 9,12, "Intel Atom (Jasper Lake)"); // LX* + // LX*. Coreboot* provides stepping. + FMS ( 0, 6, 9,12, 0, "Intel Atom (Jasper Lake A0)"); + FM ( 0, 6, 9,12, "Intel Atom (Jasper Lake)"); FM ( 0, 6, 9,13, "Intel NNP I-1000 (Spring Hill)"); // LX* // Intel docs (334663, 335718, 336466, 338014) omit the stepping numbers for // (0,6),(9,14) B0, but (337346) provides some. @@ -3328,10 +3333,12 @@ FMSQ( 0, 6, 9,14, 11, dC, "Intel Celeron G4900 (Coffee Lake B0)"); // no spec update; MRG* 2020-01-27 FMSQ( 0, 6, 9,14, 11, dP, "Intel Pentium Gold G5000 (Coffee Lake B0)"); // MRG* 2020-01-27 pinned down stepping FMSQ( 0, 6, 9,14, 12, dc, "Intel Core i*-9000 S Line (Coffee Lake P0)"); + FMSQ( 0, 6, 9,14, 13, d1, "Intel CC150 (Coffee Lake R0)"); // no docs; only instlatx64 example FMSQ( 0, 6, 9,14, 13, dc, "Intel Core i*-9000 H Line (Coffee Lake R0)"); FMSQ( 0, 6, 9,14, 13, sX, "Intel Xeon E-2200 (Coffee Lake R0)"); // no docs on stepping; only MRG 2019-11-13 FM ( 0, 6, 9,14, "Intel Core (unknown type) (Kaby Lake / Coffee Lake)"); // LX*. Coreboot* provides more detail & steppings + // (615213) mentions the (0,6),(10,5),2 stepping, but does not provide its name. FMS ( 0, 6, 10, 5, 0, "Intel (unknown model) (Comet Lake-H/S G0)"); FMS ( 0, 6, 10, 5, 1, "Intel (unknown model) (Comet Lake-H/S P0)"); FMS ( 0, 6, 10, 5, 3, "Intel (unknown model) (Comet Lake-H/S G1)"); @@ -4194,14 +4201,16 @@ // recent AMD pattern, these must be (7,15),(3,0). FMSQ( 7,15, 3, 0, 1, Sa, "AMD A-Series (Beema ML-A1)"); FMSQ( 7,15, 3, 0, 1, Se, "AMD E-Series (Beema ML-A1)"); + FMSQ( 7,15, 3, 0, 1, Sg, "AMD G-Series (Steppe Eagle/Crowned Eagle ML-A1)"); // undocumented; instlatx64 sample FMSQ( 7,15, 3, 0, 1, Ta, "AMD A-Series Micro (Mullins ML-A1)"); FMSQ( 7,15, 3, 0, 1, Te, "AMD E-Series Micro (Mullins ML-A1)"); FMS ( 7,15, 3, 0, 1, "AMD (unknown type) (Beema/Mullins ML-A1)"); FMQ ( 7,15, 3, 0, Sa, "AMD A-Series (Beema)"); FMQ ( 7,15, 3, 0, Se, "AMD E-Series (Beema)"); + FMQ ( 7,15, 3, 0, Sg, "AMD E-Series (Steppe Eagle/Crowned Eagle)"); FMQ ( 7,15, 3, 0, Ta, "AMD A-Series Micro (Mullins)"); FMQ ( 7,15, 3, 0, Te, "AMD E-Series Micro (Mullins)"); - FM ( 7,15, 3, 0, "AMD (unknown type) (Beema/Mullins)"); + FM ( 7,15, 3, 0, "AMD (unknown type) (Beema/Mullins/Steppe Eagle/Crowned Eagle)"); // sandpile.org mentions (7,15),(6,0) Puma-esque "NL" cores // (with stepping 1 = A1), but I have no idea of any such code name. F ( 7,15, "AMD (unknown model)"); @@ -4239,7 +4248,7 @@ FMS ( 8,15, 3, 1, 0, "AMD Ryzen (Castle Peak B0) / EPYC (Rome B0)"); FM ( 8,15, 3, 1, "AMD Ryzen (Castle Peak) / EPYC (Rome)"); FM ( 8,15, 5, 0, "AMD DG02SRTBP4MFA (Fenghuang 15FF)"); // internal model, only instlatx64 example - FM ( 8,15, 6, 0, "AMD Ryzen (Renoir)"); // undocumented, geekbench.com example (with stepping 1) + FM ( 8,15, 6, 0, "AMD Ryzen (Renoir)"); // undocumented, instlatx64 examples (with stepping 1) FMS ( 8,15, 7, 1, 0, "AMD Ryzen (Matisse B0)"); // undocumented, but samples from Steven Noonan FM ( 8,15, 7, 1, "AMD Ryzen (Matisse)"); // undocumented, but samples from Steven Noonan F ( 8,15, "AMD (unknown model)"); @@ -5166,7 +5175,7 @@ { static named_item names[] = { { "process local APIC physical ID" , 24, 31, NIL_IMAGES }, - { "cpu count" , 16, 23, NIL_IMAGES }, + { "maximum IDs for CPUs in pkg" , 16, 23, NIL_IMAGES }, { "CLFLUSH line size" , 8, 15, NIL_IMAGES }, { "brand index" , 0, 7, NIL_IMAGES }, }; @@ -5448,8 +5457,8 @@ { "cache level" , 5, 7, NIL_IMAGES }, { "self-initializing cache level" , 8, 8, bools }, { "fully associative cache" , 9, 9, bools }, - { "extra threads sharing this cache" , 14, 25, NIL_IMAGES }, - { "extra processor cores on this die" , 26, 31, NIL_IMAGES }, + { "maximum IDs for CPUs sharing cache" , 14, 25, NIL_IMAGES }, + { "maximum IDs for cores in pkg" , 26, 31, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), @@ -5722,7 +5731,9 @@ { "fast short REP MOV" , 4, 4, bools }, { "AVX512_VP2INTERSECT: intersect mask regs", 8, 8, bools }, { "VERW md-clear microcode support" , 10, 10, bools }, // Xen*/Qemu* + { "SERIALIZE" , 14, 14, bools }, { "hybrid part" , 15, 15, bools }, + { "TSXLDTRK: TSX suspend load addr tracking", 16, 16, bools }, { "PCONFIG instruction" , 18, 18, bools }, { "CET_IBT: CET indirect branch tracking" , 20, 20, bools }, { "IBRS/IBPB: indirect branch restrictions" , 26, 26, bools }, @@ -6005,6 +6016,17 @@ } static void +print_f_1_eax(unsigned int value) +{ + static named_item names[] + = { { "IA32_QM_CTR bit 61 is overflow" , 8, 8, bools }, + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 43); +} + +static void print_f_1_edx(unsigned int value) { static named_item names[] @@ -6014,7 +6036,7 @@ }; print_names(value, names, LENGTH(names), - /* max_len => */ 0); + /* max_len => */ 43); } static void @@ -6079,7 +6101,8 @@ print_10_3_ecx(unsigned int value) { static named_item names[] - = { { "delay values are linear" , 2, 2, bools }, + = { { "per-thread MBA control" , 0, 0, bools }, + { "delay values are linear" , 2, 2, bools }, }; print_names(value, names, LENGTH(names), @@ -6156,7 +6179,7 @@ }; print_names(value, names, LENGTH(names), - /* max_len => */ 0); + /* max_len => */ 38); } static void @@ -6171,7 +6194,7 @@ }; print_names(value, names, LENGTH(names), - /* max_len => */ 0); + /* max_len => */ 38); } static void @@ -6183,7 +6206,7 @@ }; print_names(value, names, LENGTH(names), - /* max_len => */ 0); + /* max_len => */ 38); } static void @@ -6195,7 +6218,7 @@ }; print_names(value, names, LENGTH(names), - /* max_len => */ 0); + /* max_len => */ 38); } static void @@ -7454,7 +7477,7 @@ { "WBNOINVD instruction" , 9, 9, bools }, { "IBPB: indirect branch prediction barrier", 12, 12, bools }, { "IBRS: indirect branch restr speculation" , 14, 14, bools }, - { "STIBP: 1 thr indirect branch predictor" , 15, 15, bools }, + { "STIBP: 1 thr indirect branch predictor" , 15, 15, bools }, // Qemu* { "STIBP always on preferred mode" , 17, 17, bools }, // LX* { "ppin processor id number supported" , 23, 23, bools }, // Xen* { "SSBD: speculative store bypass disable" , 24, 24, bools }, @@ -7797,6 +7820,14 @@ { "SEV: secure encrypted virtualize support", 1, 1, bools }, { "VM page flush MSR support" , 2, 2, bools }, { "SEV-ES: SEV encrypted state support" , 3, 3, bools }, + { "SEV-SNP: SEV secure nested paging" , 4, 4, bools }, + { "VMPL: VM permission levels" , 5, 5, bools }, + { "hardware cache coher across enc domains" , 10, 10, bools }, + { "SEV guest exec only from 64-bit host" , 11, 11, bools }, + { "restricted injection" , 12, 12, bools }, + { "alternate injection" , 13, 13, bools }, + { "full debug state swap for SEV-ES guests" , 14, 14, bools }, + { "disallowing IBS use by host" , 15, 15, bools }, }; print_names(value, names, LENGTH(names), @@ -7809,6 +7840,7 @@ static named_item names[] = { { "encryption bit position in PTE" , 0, 5, NIL_IMAGES }, { "physical address space width reduction" , 6, 11, NIL_IMAGES }, + { "number of VM permission levels" , 12, 15, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); @@ -8411,6 +8443,9 @@ words[WORD_EBX]); printf(" Maximum range of RMID = %u\n", words[WORD_ECX]); + printf(" Counter width = %u\n", + 24 + BIT_EXTRACT_LE(words[WORD_EAX], 0, 8)); + print_f_1_eax(words[WORD_EAX]); print_f_1_edx(words[WORD_EDX]); } else { print_reg_raw(reg, try, words); diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20200211/cpuid.man new/cpuid-20200427/cpuid.man --- old/cpuid-20200211/cpuid.man 2020-02-11 10:36:05.000000000 +0100 +++ new/cpuid-20200427/cpuid.man 2020-04-27 14:10:13.000000000 +0200 @@ -1,7 +1,7 @@ .\" -.\" $Id: cpuid.man,v 20200211 2020/02/11 02:36:00 todd $ +.\" $Id: cpuid.man,v 20200211 2020/04/27 06:09:42 todd $ .\" -.TH CPUID 1 "11 Feb 2020" "20200211" +.TH CPUID 1 "27 Apr 2020" "20200427" .SH NAME cpuid \- Dump CPUID information for each CPU .SH SYNOPSIS @@ -525,6 +525,9 @@ .br 24332: AMD Athlon Processor Model 6 Revision Guide .br +24594: AMD64 Architecture Programmer's Manual Volume 3: +General-Purpose and System Instructions +.br 24806: AMD Duron Processor Model 7 Revision Guide .br 25481: CPUID Specification @@ -544,6 +547,8 @@ .br 33234F: AMD Geode LX Processors Data Book .br +40332: AMD64 Architecture Programmer's Manual: Volumes 1-5 +.br 41322: Revision Guide for AMD Family 10h Processors .br 41788: Revision Guide for AMD Family 11h Processors diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20200211/cpuid.spec new/cpuid-20200427/cpuid.spec --- old/cpuid-20200211/cpuid.spec 2020-02-11 10:39:07.000000000 +0100 +++ new/cpuid-20200427/cpuid.spec 2020-04-27 14:11:59.000000000 +0200 @@ -1,4 +1,4 @@ -%define version 20200211 +%define version 20200427 %define release 1 Summary: dumps CPUID information about the CPU(s) Name: cpuid
