Hello community,
here is the log from the commit of package u-boot for openSUSE:Leap:15.2
checked in at 2020-05-07 19:29:01
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Comparing /work/SRC/openSUSE:Leap:15.2/u-boot (Old)
and /work/SRC/openSUSE:Leap:15.2/.u-boot.new.2738 (New)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "u-boot"
Thu May 7 19:29:01 2020 rev:59 rq:801260 version:2020.01
Changes:
--------
--- /work/SRC/openSUSE:Leap:15.2/u-boot/u-boot.changes 2020-04-17
13:37:33.452220520 +0200
+++ /work/SRC/openSUSE:Leap:15.2/.u-boot.new.2738/u-boot.changes
2020-05-07 19:38:10.322790469 +0200
@@ -1,0 +2,26 @@
+Wed May 6 07:39:58 UTC 2020 - Matthias Brugger <mbrug...@suse.com>
+
+- Enable USB on RPi4 (jsc#SLE-12150)
+Patch queue updated from git://github.com/openSUSE/u-boot.git sle15-sp2
+* Patches added:
+ 0022-usb-xhci-Add-missing-cache-flush-in.patch
+ 0023-usb-xhci-Use-only-32-bit-accesses-i.patch
+ 0024-pci-Move-some-PCIe-register-offset-.patch
+ 0025-rpi4-shorten-a-mapping-for-the-DRAM.patch
+ 0026-rpi4-add-a-mapping-for-the-PCIe-XHC.patch
+ 0027-linux-bitfield.h-Add-primitives-for.patch
+ 0028-pci-Add-some-PCI-Express-capability.patch
+ 0029-pci-Add-driver-for-Broadcom-STB-PCI.patch
+ 0030-config-Enable-support-for-the-XHCI-.patch
+ 0031-arm-rpi-Add-function-to-trigger-VL8.patch
+ 0032-usb-xhci-Load-Raspberry-Pi-4-VL805-.patch
+
+-------------------------------------------------------------------
+Mon May 4 16:31:16 UTC 2020 - Matthias Brugger <mbrug...@suse.com>
+
+Fix grub2 console (bsc#1166971, bsc#1160464)
+Patch queue updated from git://github.com/openSUSE/u-boot.git sle15-sp2
+* Patches added:
+ 0021-efi_loader-imply-VIDEO_ANSI.patch
+
+-------------------------------------------------------------------
New:
----
0021-efi_loader-imply-VIDEO_ANSI.patch
0022-usb-xhci-Add-missing-cache-flush-in.patch
0023-usb-xhci-Use-only-32-bit-accesses-i.patch
0024-pci-Move-some-PCIe-register-offset-.patch
0025-rpi4-shorten-a-mapping-for-the-DRAM.patch
0026-rpi4-add-a-mapping-for-the-PCIe-XHC.patch
0027-linux-bitfield.h-Add-primitives-for.patch
0028-pci-Add-some-PCI-Express-capability.patch
0029-pci-Add-driver-for-Broadcom-STB-PCI.patch
0030-config-Enable-support-for-the-XHCI-.patch
0031-arm-rpi-Add-function-to-trigger-VL8.patch
0032-usb-xhci-Load-Raspberry-Pi-4-VL805-.patch
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Other differences:
------------------
++++++ u-boot.spec ++++++
--- /var/tmp/diff_new_pack.m25LUr/_old 2020-05-07 19:38:12.082793991 +0200
+++ /var/tmp/diff_new_pack.m25LUr/_new 2020-05-07 19:38:12.082793991 +0200
@@ -221,6 +221,18 @@
Patch0018: 0018-net-bcmgenet-Don-t-set-ID_MODE_DIS-.patch
Patch0019: 0019-uboot-fs-btrfs-Use-LZO_LEN-to-repla.patch
Patch0020: 0020-uboot-fs-btrfs-Fix-LZO-false-decomp.patch
+Patch0021: 0021-efi_loader-imply-VIDEO_ANSI.patch
+Patch0022: 0022-usb-xhci-Add-missing-cache-flush-in.patch
+Patch0023: 0023-usb-xhci-Use-only-32-bit-accesses-i.patch
+Patch0024: 0024-pci-Move-some-PCIe-register-offset-.patch
+Patch0025: 0025-rpi4-shorten-a-mapping-for-the-DRAM.patch
+Patch0026: 0026-rpi4-add-a-mapping-for-the-PCIe-XHC.patch
+Patch0027: 0027-linux-bitfield.h-Add-primitives-for.patch
+Patch0028: 0028-pci-Add-some-PCI-Express-capability.patch
+Patch0029: 0029-pci-Add-driver-for-Broadcom-STB-PCI.patch
+Patch0030: 0030-config-Enable-support-for-the-XHCI-.patch
+Patch0031: 0031-arm-rpi-Add-function-to-trigger-VL8.patch
+Patch0032: 0032-usb-xhci-Load-Raspberry-Pi-4-VL805-.patch
# Patches: end
BuildRequires: bc
BuildRequires: bison
++++++ 0021-efi_loader-imply-VIDEO_ANSI.patch ++++++
>From bb1b7896523272adc3139b9c8f17f008273b1e73 Mon Sep 17 00:00:00 2001
From: Heinrich Schuchardt <xypron.g...@gmx.de>
Date: Wed, 15 Jan 2020 00:49:35 +0100
Subject: [PATCH] efi_loader: imply VIDEO_ANSI
UEFI programs like GRUB make change terminal colors which requires support
for ANSI escape sequences.
Let CONFIG_EFI_LOADER=y imply CONFIG_VIDEO_ANSI.
Signed-off-by: Heinrich Schuchardt <xypron.g...@gmx.de>
---
lib/efi_loader/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 21ef440341..5016a61f49 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -15,6 +15,7 @@ config EFI_LOADER
select HAVE_BLOCK_DEVICE
select REGEX
imply CFB_CONSOLE_ANSI
+ imply VIDEO_ANSI
help
Select this option if you want to run UEFI applications (like GNU
GRUB or iPXE) on top of U-Boot. If this option is enabled, U-Boot
++++++ 0022-usb-xhci-Add-missing-cache-flush-in.patch ++++++
>From 92a2d04e443ce6e8b68e8746a745e688a094681f Mon Sep 17 00:00:00 2001
From: Sylwester Nawrocki <s.nawro...@samsung.com>
Date: Mon, 4 May 2020 14:45:14 +0200
Subject: [PATCH] usb: xhci: Add missing cache flush in the scratchpad array
initialization
In current code there is no cache flush after initializing the scratchpad
buffer array with the scratchpad buffer pointers. This leads to a failure
of the "slot enable" command on the rpi4 board (Broadcom STB PCIe
controller + VL805 USB hub) - the very first TRB transfer on the command
ring fails and there is a timeout while waiting for the command completion
event. After adding the missing cache flush everything seems to be working
as expected.
Signed-off-by: Sylwester Nawrocki <s.nawro...@samsung.com>
Reviewed-by: Bin Meng <bmeng...@gmail.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulie...@suse.de>
---
drivers/usb/host/xhci-mem.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index 93450ee3b7..729bdc3c84 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -393,6 +393,9 @@ static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl)
scratchpad->sp_array[i] = cpu_to_le64(ptr);
}
+ xhci_flush_cache((uintptr_t)scratchpad->sp_array,
+ sizeof(u64) * num_sp);
+
return 0;
fail_sp3:
++++++ 0023-usb-xhci-Use-only-32-bit-accesses-i.patch ++++++
>From 42e35c6b2f72c6395e4517775c13a9f9675f9ca8 Mon Sep 17 00:00:00 2001
From: Sylwester Nawrocki <s.nawro...@samsung.com>
Date: Mon, 4 May 2020 14:45:15 +0200
Subject: [PATCH] usb: xhci: Use only 32-bit accesses in xhci_writeq/xhci_readq
There might be hardware configurations where 64-bit data accesses
to XHCI registers are not supported properly. This patch removes
the readq/writeq so always two 32-bit accesses are used to read/write
64-bit XHCI registers, similarly as it is done in Linux kernel.
This patch fixes operation of the XHCI controller on RPI4 Broadcom
BCM2711 SoC based board, where the VL805 USB XHCI controller is
connected to the PCIe Root Complex, which is attached to the system
through the SCB bridge.
Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely
the 64-bit wide register accesses initiated by the CPU are not properly
translated to a sequence of 32-bit PCIe accesses.
xhci_readq(), for example, always returns same value in upper and lower
32-bits, e.g. 0xabcd1234abcd1234 instead of 0x00000000abcd1234.
Cc: Sergey Temerkhanov <s.temerkha...@gmail.com>
Signed-off-by: Sylwester Nawrocki <s.nawro...@samsung.com>
Reviewed-by: Bin Meng <bmeng...@gmail.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulie...@suse.de>
---
include/usb/xhci.h | 8 --------
1 file changed, 8 deletions(-)
diff --git a/include/usb/xhci.h b/include/usb/xhci.h
index 6017504488..c16106a2fc 100644
--- a/include/usb/xhci.h
+++ b/include/usb/xhci.h
@@ -1111,28 +1111,20 @@ static inline void xhci_writel(uint32_t volatile *regs,
const unsigned int val)
*/
static inline u64 xhci_readq(__le64 volatile *regs)
{
-#if BITS_PER_LONG == 64
- return readq(regs);
-#else
__u32 *ptr = (__u32 *)regs;
u64 val_lo = readl(ptr);
u64 val_hi = readl(ptr + 1);
return val_lo + (val_hi << 32);
-#endif
}
static inline void xhci_writeq(__le64 volatile *regs, const u64 val)
{
-#if BITS_PER_LONG == 64
- writeq(val, regs);
-#else
__u32 *ptr = (__u32 *)regs;
u32 val_lo = lower_32_bits(val);
/* FIXME */
u32 val_hi = upper_32_bits(val);
writel(val_lo, ptr);
writel(val_hi, ptr + 1);
-#endif
}
int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr,
++++++ 0024-pci-Move-some-PCIe-register-offset-.patch ++++++
>From 656aa6fbd03a85ee6dcb2797dbc9e35231ec1cf0 Mon Sep 17 00:00:00 2001
From: Sylwester Nawrocki <s.nawro...@samsung.com>
Date: Mon, 4 May 2020 14:45:16 +0200
Subject: [PATCH] pci: Move some PCIe register offset definitions to a common
header
Some PCI Express register offsets are currently defined in multiple
drivers, move them to a common header to avoid re-definitions and
as a pre-requisite for adding new PCIe driver.
While at it replace some spaces with tabs.
Signed-off-by: Sylwester Nawrocki <s.nawro...@samsung.com>
Reviewed-by: Bin Meng <bmeng...@gmail.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulie...@suse.de>
---
drivers/pci/pci-rcar-gen3.c | 8 --------
drivers/pci/pcie_intel_fpga.c | 3 ---
include/pci.h | 13 +++++++++++--
3 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c
index 52ca13b70c..0cfa2b8526 100644
--- a/drivers/pci/pci-rcar-gen3.c
+++ b/drivers/pci/pci-rcar-gen3.c
@@ -117,14 +117,6 @@
#define RCAR_PCI_MAX_RESOURCES 4
#define MAX_NR_INBOUND_MAPS 6
-#define PCI_EXP_FLAGS 2 /* Capabilities register */
-#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
-#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
-#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
-#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active
Reporting Capable */
-#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
-#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
-
enum {
RCAR_PCI_ACCESS_READ,
RCAR_PCI_ACCESS_WRITE,
diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c
index a5ea4888f3..5da4d1c26c 100644
--- a/drivers/pci/pcie_intel_fpga.c
+++ b/drivers/pci/pcie_intel_fpga.c
@@ -64,9 +64,6 @@
#define IS_ROOT_PORT(pcie, bdf) \
((PCI_BUS(bdf) == pcie->first_busno) ? true : false)
-#define PCI_EXP_LNKSTA 18 /* Link Status */
-#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
-
/**
* struct intel_fpga_pcie - Intel FPGA PCIe controller state
* @bus: Pointer to the PCI bus
diff --git a/include/pci.h b/include/pci.h
index ff59ac0e69..1c7e4818ea 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -471,10 +471,19 @@
#define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */
/* PCI Express capabilities */
+#define PCI_EXP_FLAGS 2 /* Capabilities register */
+#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
+#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
#define PCI_EXP_DEVCAP 4 /* Device capabilities */
-#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */
+#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */
#define PCI_EXP_DEVCTL 8 /* Device Control */
-#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
+#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry /
FLR */
+#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
+#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link
Active Reporting Capable */
+#define PCI_EXP_LNKSTA 18 /* Link Status */
+#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
+#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
+#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
/* Include the ID list */
++++++ 0025-rpi4-shorten-a-mapping-for-the-DRAM.patch ++++++
>From 3ab38989cdf0aaae237f8b2f474d863be1ecc62a Mon Sep 17 00:00:00 2001
From: Marek Szyprowski <m.szyprow...@samsung.com>
Date: Mon, 4 May 2020 14:45:17 +0200
Subject: [PATCH] rpi4: shorten a mapping for the DRAM
Remove the overlap between DRAM and device's IO area.
Signed-off-by: Marek Szyprowski <m.szyprow...@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawro...@samsung.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulie...@suse.de>
---
arch/arm/mach-bcm283x/init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index 9966d6c833..42953561a7 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -38,7 +38,7 @@ static struct mm_region bcm2711_mem_map[] = {
{
.virt = 0x00000000UL,
.phys = 0x00000000UL,
- .size = 0xfe000000UL,
+ .size = 0xfc000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
++++++ 0026-rpi4-add-a-mapping-for-the-PCIe-XHC.patch ++++++
>From 79fa8b6df328a35f63046ac155ed4ab33fa78d66 Mon Sep 17 00:00:00 2001
From: Marek Szyprowski <m.szyprow...@samsung.com>
Date: Mon, 4 May 2020 14:45:18 +0200
Subject: [PATCH] rpi4: add a mapping for the PCIe XHCI controller MMIO
registers (ARM 64bit)
Create a non-cacheable mapping for the 0x600000000 physical memory region,
where MMIO registers for the PCIe XHCI controller are instantiated by the
PCIe bridge.
Signed-off-by: Marek Szyprowski <m.szyprow...@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawro...@samsung.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulie...@suse.de>
---
arch/arm/mach-bcm283x/init.c | 18 +++++++++++++++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index 42953561a7..6a748da171 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -11,10 +11,15 @@
#include <dm/device.h>
#include <fdt_support.h>
+#define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS 0x600000000UL
+#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE 0x800000UL
+
#ifdef CONFIG_ARM64
#include <asm/armv8/mmu.h>
-static struct mm_region bcm283x_mem_map[] = {
+#define MAX_MAP_MAX_ENTRIES (4)
+
+static struct mm_region bcm283x_mem_map[MAX_MAP_MAX_ENTRIES] = {
{
.virt = 0x00000000UL,
.phys = 0x00000000UL,
@@ -34,7 +39,7 @@ static struct mm_region bcm283x_mem_map[] = {
}
};
-static struct mm_region bcm2711_mem_map[] = {
+static struct mm_region bcm2711_mem_map[MAX_MAP_MAX_ENTRIES] = {
{
.virt = 0x00000000UL,
.phys = 0x00000000UL,
@@ -48,6 +53,13 @@ static struct mm_region bcm2711_mem_map[] = {
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
+ .phys = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
+ .size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
@@ -71,7 +83,7 @@ static void _rpi_update_mem_map(struct mm_region *pd)
{
int i;
- for (i = 0; i < 2; i++) {
+ for (i = 0; i < MAX_MAP_MAX_ENTRIES; i++) {
mem_map[i].virt = pd[i].virt;
mem_map[i].phys = pd[i].phys;
mem_map[i].size = pd[i].size;
++++++ 0027-linux-bitfield.h-Add-primitives-for.patch ++++++
>From 25073d1f4beeb4eb4d2917207e9c5862b7629e0d Mon Sep 17 00:00:00 2001
From: Nicolas Saenz Julienne <nsaenzjulie...@suse.de>
Date: Mon, 4 May 2020 14:45:20 +0200
Subject: [PATCH] linux/bitfield.h: Add primitives for manipulating bitfields
both in host- and fixed-endian
Imports Al Viro's original Linux commit 00b0c9b82663a, which contains
an in depth explanation and two fixes from Johannes Berg:
e7d4a95da86e0 "bitfield: fix *_encode_bits()",
37a3862e12382 "bitfield: add u8 helpers".
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulie...@suse.de>
[s.nawrocki: added empty lines between functions and macros]
Signed-off-by: Sylwester Nawrocki <s.nawro...@samsung.com>
---
include/linux/bitfield.h | 50 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h
index 8b9d6fff00..7acba4c524 100644
--- a/include/linux/bitfield.h
+++ b/include/linux/bitfield.h
@@ -103,4 +103,54 @@
(typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
})
+extern void __compiletime_error("value doesn't fit into mask")
+__field_overflow(void);
+extern void __compiletime_error("bad bitfield mask")
+__bad_mask(void);
+static __always_inline u64 field_multiplier(u64 field)
+{
+ if ((field | (field - 1)) & ((field | (field - 1)) + 1))
+ __bad_mask();
+ return field & -field;
+}
+static __always_inline u64 field_mask(u64 field)
+{
+ return field / field_multiplier(field);
+}
+
+#define ____MAKE_OP(type,base,to,from) \
+static __always_inline __##type type##_encode_bits(base v, base field) \
+{ \
+ if (__builtin_constant_p(v) && (v & ~field_mask(field))) \
+ __field_overflow(); \
+ return to((v & field_mask(field)) * field_multiplier(field)); \
+} \
+static __always_inline __##type type##_replace_bits(__##type old, \
+ base val, base field) \
+{ \
+ return (old & ~to(field)) | type##_encode_bits(val, field); \
+} \
+static __always_inline void type##p_replace_bits(__##type *p, \
+ base val, base field) \
+{ \
+ *p = (*p & ~to(field)) | type##_encode_bits(val, field); \
+} \
+static __always_inline base type##_get_bits(__##type v, base field) \
+{ \
+ return (from(v) & field)/field_multiplier(field); \
+}
+
+#define __MAKE_OP(size)
\
+ ____MAKE_OP(le##size,u##size,cpu_to_le##size,le##size##_to_cpu) \
+ ____MAKE_OP(be##size,u##size,cpu_to_be##size,be##size##_to_cpu) \
+ ____MAKE_OP(u##size,u##size,,)
+
+____MAKE_OP(u8,u8,,)
+__MAKE_OP(16)
+__MAKE_OP(32)
+__MAKE_OP(64)
+
+#undef __MAKE_OP
+#undef ____MAKE_OP
+
#endif
++++++ 0028-pci-Add-some-PCI-Express-capability.patch ++++++
>From d902cacdb28383f912fd7ad180bdc0f5dbe3469a Mon Sep 17 00:00:00 2001
From: Sylwester Nawrocki <s.nawro...@samsung.com>
Date: Mon, 4 May 2020 14:45:21 +0200
Subject: [PATCH] pci: Add some PCI Express capability register offset
definitions
Add PCI Express capability definitions required by the Broadcom
STB PCIe controller driver.
Signed-off-by: Sylwester Nawrocki <s.nawro...@samsung.com>
Reviewed-by: Bin Meng <bmeng...@gmail.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulie...@suse.de>
---
include/pci.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/include/pci.h b/include/pci.h
index 1c7e4818ea..4b8a1f207c 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -479,11 +479,17 @@
#define PCI_EXP_DEVCTL 8 /* Device Control */
#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry /
FLR */
#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
+#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */
+#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link
Active Reporting Capable */
#define PCI_EXP_LNKSTA 18 /* Link Status */
+#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */
+#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */
+#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */
#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
+#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
/* Include the ID list */
++++++ 0029-pci-Add-driver-for-Broadcom-STB-PCI.patch ++++++
++++ 646 lines (skipped)
++++++ 0030-config-Enable-support-for-the-XHCI-.patch ++++++
>From fc6568b85a2320837c9ee72773d03382624ccb06 Mon Sep 17 00:00:00 2001
From: Marek Szyprowski <m.szyprow...@samsung.com>
Date: Mon, 4 May 2020 14:45:23 +0200
Subject: [PATCH] config: Enable support for the XHCI controller on RPI4 board
This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI
and USB commands. To get it working one has to call the following commands:
"pci enum; usb start;", thus such commands have been added to the default
"preboot" environment variable. One has to update their environment if it
is already configured to get this feature working out of the box.
Signed-off-by: Marek Szyprowski <m.szyprow...@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawro...@samsung.com>
---
configs/rpi_4_32b_defconfig | 11 +++++++++++
configs/rpi_4_defconfig | 11 +++++++++++
configs/rpi_arm64_defconfig | 8 +++++++-
3 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig
index e7ea88bd4b..9a0e23368d 100644
--- a/configs/rpi_4_32b_defconfig
+++ b/configs/rpi_4_32b_defconfig
@@ -8,12 +8,16 @@ CONFIG_NR_DRAM_BANKS=2
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="pci enum; usb start;"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
CONFIG_CMD_FS_UUID=y
CONFIG_OF_BOARD=y
CONFIG_ENV_FAT_INTERFACE="mmc"
@@ -26,9 +30,16 @@ CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCM2835=y
CONFIG_DM_ETH=y
CONFIG_BCMGENET=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_BRCMSTB=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_BPP32=y
CONFIG_SYS_WHITE_ON_BLACK=y
diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig
index b0f9cf1c0e..6dfb69e797 100644
--- a/configs/rpi_4_defconfig
+++ b/configs/rpi_4_defconfig
@@ -8,12 +8,16 @@ CONFIG_NR_DRAM_BANKS=2
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="pci enum; usb start;"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
CONFIG_CMD_FS_UUID=y
CONFIG_OF_BOARD=y
CONFIG_ENV_FAT_INTERFACE="mmc"
@@ -26,9 +30,16 @@ CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCM2835=y
CONFIG_DM_ETH=y
CONFIG_BCMGENET=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_BRCMSTB=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_BPP32=y
CONFIG_SYS_WHITE_ON_BLACK=y
diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig
index 00b3096481..4083cabdd3 100644
--- a/configs/rpi_arm64_defconfig
+++ b/configs/rpi_arm64_defconfig
@@ -7,13 +7,14 @@ CONFIG_NR_DRAM_BANKS=2
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
-CONFIG_PREBOOT="usb start"
+CONFIG_PREBOOT="pci enum; usb start;"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_FS_UUID=y
CONFIG_OF_BOARD=y
@@ -26,11 +27,16 @@ CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCM2835=y
CONFIG_PHYLIB=y
CONFIG_DM_ETH=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_BRCMSTB=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
CONFIG_USB_DWC2=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
++++++ 0031-arm-rpi-Add-function-to-trigger-VL8.patch ++++++
>From cfa03909f2bcec19f7242b446b6fb9dfdbf2fa3e Mon Sep 17 00:00:00 2001
From: Nicolas Saenz Julienne <nsaenzjulie...@suse.de>
Date: Tue, 5 May 2020 18:26:06 +0200
Subject: [PATCH] arm: rpi: Add function to trigger VL805's firmware load
On the Raspberry Pi 4, after a PCI reset, VL805's (a xHCI chip) firmware
may either be loaded directly from an EEPROM or, if not present, by the
SoC's VideCore (the SoC's co-processor). Introduce the function that
informs VideCore that VL805 may need its firmware loaded.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulie...@suse.de>
---
arch/arm/mach-bcm283x/include/mach/mbox.h | 13 +++++++
arch/arm/mach-bcm283x/include/mach/msg.h | 7 ++++
arch/arm/mach-bcm283x/msg.c | 45 +++++++++++++++++++++++
3 files changed, 65 insertions(+)
diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h
b/arch/arm/mach-bcm283x/include/mach/mbox.h
index 60e226ce1d..2ae2d3d97c 100644
--- a/arch/arm/mach-bcm283x/include/mach/mbox.h
+++ b/arch/arm/mach-bcm283x/include/mach/mbox.h
@@ -491,6 +491,19 @@ struct bcm2835_mbox_tag_set_palette {
} body;
};
+#define BCM2835_MBOX_TAG_NOTIFY_XHCI_RESET 0x00030058
+
+struct bcm2835_mbox_tag_pci_dev_addr {
+ struct bcm2835_mbox_tag_hdr tag_hdr;
+ union {
+ struct {
+ u32 dev_addr;
+ } req;
+ struct {
+ } resp;
+ } body;
+};
+
/*
* Pass a raw u32 message to the VC, and receive a raw u32 back.
*
diff --git a/arch/arm/mach-bcm283x/include/mach/msg.h
b/arch/arm/mach-bcm283x/include/mach/msg.h
index 4afb08631b..f5213dd0e0 100644
--- a/arch/arm/mach-bcm283x/include/mach/msg.h
+++ b/arch/arm/mach-bcm283x/include/mach/msg.h
@@ -48,4 +48,11 @@ int bcm2835_set_video_params(int *widthp, int *heightp, int
depth_bpp,
int pixel_order, int alpha_mode, ulong *fb_basep,
ulong *fb_sizep, int *pitchp);
+/**
+ * bcm2711_notify_vl805_reset() - get vl805's firmware loaded
+ *
+ * @return 0 if OK, -EIO on error
+ */
+int bcm2711_notify_vl805_reset(void);
+
#endif
diff --git a/arch/arm/mach-bcm283x/msg.c b/arch/arm/mach-bcm283x/msg.c
index 94b75283f8..f8ef531652 100644
--- a/arch/arm/mach-bcm283x/msg.c
+++ b/arch/arm/mach-bcm283x/msg.c
@@ -40,6 +40,12 @@ struct msg_setup {
u32 end_tag;
};
+struct msg_notify_vl805_reset {
+ struct bcm2835_mbox_hdr hdr;
+ struct bcm2835_mbox_tag_pci_dev_addr dev_addr;
+ u32 end_tag;
+};
+
int bcm2835_power_on_module(u32 module)
{
ALLOC_CACHE_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1);
@@ -151,3 +157,42 @@ int bcm2835_set_video_params(int *widthp, int *heightp,
int depth_bpp,
return 0;
}
+
+/*
+ * The Raspberry Pi 4 gets its USB functionality from VL805, a PCIe chip that
+ * implements xHCI. After a PCI reset, VL805's firmware may either be loaded
+ * directly from an EEPROM or, if not present, by the SoC's co-processor,
+ * VideoCore. RPi4's VideoCore OS contains both the non public firmware load
+ * logic and the VL805 firmware blob. This function triggers the aforementioned
+ * process.
+ */
+int bcm2711_notify_vl805_reset(void)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(struct msg_notify_vl805_reset,
+ msg_notify_vl805_reset, 1);
+ int ret;
+
+ BCM2835_MBOX_INIT_HDR(msg_notify_vl805_reset);
+ BCM2835_MBOX_INIT_TAG(&msg_notify_vl805_reset->dev_addr,
+ NOTIFY_XHCI_RESET);
+
+ /*
+ * The pci device address is expected like this:
+ *
+ * PCI_BUS << 20 | PCI_SLOT << 15 | PCI_FUNC << 12
+ *
+ * But since RPi4's PCIe setup is hardwired, we know the address in
+ * advance.
+ */
+ msg_notify_vl805_reset->dev_addr.body.req.dev_addr = 0x100000;
+
+ ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN,
+ &msg_notify_vl805_reset->hdr);
+ if (ret) {
+ printf("bcm2711: Faild to load vl805's firmware, %d\n", ret);
+ return -EIO;
+ }
+
+ return 0;
+}
+
++++++ 0032-usb-xhci-Load-Raspberry-Pi-4-VL805-.patch ++++++
>From 0ebaec654e080ebd9c07291a7ad9d3569d049dee Mon Sep 17 00:00:00 2001
From: Nicolas Saenz Julienne <nsaenzjulie...@suse.de>
Date: Tue, 5 May 2020 18:26:07 +0200
Subject: [PATCH] usb: xhci: Load Raspberry Pi 4 VL805's firmware
When needed, RPi4's co-processor (called VideoCore) has to be instructed
to load VL805's firmware (the chip providing xHCI support). VideCore's
firmware expects the board's PCIe bus to be already configured in order
for it to load the xHCI chip firmware. So we have to make sure this
happens in between the PCIe configuration and xHCI startup.
Introduce a callback in xhci_pci_probe() to run this platform specific
routine.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulie...@suse.de>
---
board/raspberrypi/rpi/rpi.c | 6 ++++++
drivers/usb/host/xhci-pci.c | 6 ++++++
include/usb/xhci.h | 3 +++
3 files changed, 15 insertions(+)
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index e367ba3092..dcaf45fbf2 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -14,6 +14,7 @@
#include <lcd.h>
#include <memalign.h>
#include <mmc.h>
+#include <usb/xhci.h>
#include <asm/gpio.h>
#include <asm/arch/mbox.h>
#include <asm/arch/msg.h>
@@ -494,3 +495,8 @@ int ft_board_setup(void *blob, bd_t *bd)
return 0;
}
+
+void xhci_pci_fixup(struct udevice *dev)
+{
+ bcm2711_notify_vl805_reset();
+}
diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
index c1f60da541..1285dde1ef 100644
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -11,6 +11,10 @@
#include <usb.h>
#include <usb/xhci.h>
+__weak void xhci_pci_fixup(struct udevice *dev)
+{
+}
+
static void xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr,
struct xhci_hcor **ret_hcor)
{
@@ -40,6 +44,8 @@ static int xhci_pci_probe(struct udevice *dev)
struct xhci_hccr *hccr;
struct xhci_hcor *hcor;
+ xhci_pci_fixup(dev);
+
xhci_pci_init(dev, &hccr, &hcor);
return xhci_register(dev, hccr, hcor);
diff --git a/include/usb/xhci.h b/include/usb/xhci.h
index c16106a2fc..57feed7603 100644
--- a/include/usb/xhci.h
+++ b/include/usb/xhci.h
@@ -16,6 +16,7 @@
#ifndef HOST_XHCI_H_
#define HOST_XHCI_H_
+#include <usb.h>
#include <asm/types.h>
#include <asm/cache.h>
#include <asm/io.h>
@@ -1281,4 +1282,6 @@ extern struct dm_usb_ops xhci_usb_ops;
struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev);
+extern void xhci_pci_fixup(struct udevice *dev);
+
#endif /* HOST_XHCI_H_ */
