Hello community, here is the log from the commit of package u-boot for openSUSE:Factory checked in at 2020-05-12 22:29:38 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/u-boot (Old) and /work/SRC/openSUSE:Factory/.u-boot.new.2738 (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "u-boot" Tue May 12 22:29:38 2020 rev:130 rq:802706 version:2020.04 Changes: -------- --- /work/SRC/openSUSE:Factory/u-boot/u-boot.changes 2020-04-21 13:08:44.924582700 +0200 +++ /work/SRC/openSUSE:Factory/.u-boot.new.2738/u-boot.changes 2020-05-12 22:31:57.787823177 +0200 @@ -1,0 +2,19 @@ +Mon May 11 13:40:32 UTC 2020 - Matthias Brugger <[email protected]> + +- Enable USB and USB keyboard on RPi4: +Patch queue updated from git://github.com/openSUSE/u-boot.git tumbleweed-2020.04 +* Patches added: + 0014-usb-xhci-Add-missing-cache-flush-in.patch + 0015-usb-xhci-Use-only-32-bit-accesses-i.patch + 0016-pci-Move-some-PCIe-register-offset-.patch + 0017-rpi4-shorten-a-mapping-for-the-DRAM.patch + 0018-rpi4-add-a-mapping-for-the-PCIe-XHC.patch + 0019-linux-bitfield.h-Add-primitives-for.patch + 0020-pci-Add-some-PCI-Express-capability.patch + 0021-pci-Add-driver-for-Broadcom-STB-PCI.patch + 0022-config-Enable-support-for-the-XHCI-.patch + 0023-arm-rpi-Add-function-to-trigger-VL8.patch + 0024-usb-xhci-Load-Raspberry-Pi-4-VL805-.patch + 0025-config-Enable-USB-Keyboard-support-.patch + +------------------------------------------------------------------- New: ---- 0014-usb-xhci-Add-missing-cache-flush-in.patch 0015-usb-xhci-Use-only-32-bit-accesses-i.patch 0016-pci-Move-some-PCIe-register-offset-.patch 0017-rpi4-shorten-a-mapping-for-the-DRAM.patch 0018-rpi4-add-a-mapping-for-the-PCIe-XHC.patch 0019-linux-bitfield.h-Add-primitives-for.patch 0020-pci-Add-some-PCI-Express-capability.patch 0021-pci-Add-driver-for-Broadcom-STB-PCI.patch 0022-config-Enable-support-for-the-XHCI-.patch 0023-arm-rpi-Add-function-to-trigger-VL8.patch 0024-usb-xhci-Load-Raspberry-Pi-4-VL805-.patch 0025-config-Enable-USB-Keyboard-support-.patch ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ u-boot.spec ++++++ --- /var/tmp/diff_new_pack.ikt5KL/_old 2020-05-12 22:32:01.135830163 +0200 +++ /var/tmp/diff_new_pack.ikt5KL/_new 2020-05-12 22:32:01.139830172 +0200 @@ -216,6 +216,18 @@ Patch0011: 0011-net-bcmgenet-Don-t-set-ID_MODE_DIS-.patch Patch0012: 0012-uboot-fs-btrfs-Use-LZO_LEN-to-repla.patch Patch0013: 0013-uboot-fs-btrfs-Fix-LZO-false-decomp.patch +Patch0014: 0014-usb-xhci-Add-missing-cache-flush-in.patch +Patch0015: 0015-usb-xhci-Use-only-32-bit-accesses-i.patch +Patch0016: 0016-pci-Move-some-PCIe-register-offset-.patch +Patch0017: 0017-rpi4-shorten-a-mapping-for-the-DRAM.patch +Patch0018: 0018-rpi4-add-a-mapping-for-the-PCIe-XHC.patch +Patch0019: 0019-linux-bitfield.h-Add-primitives-for.patch +Patch0020: 0020-pci-Add-some-PCI-Express-capability.patch +Patch0021: 0021-pci-Add-driver-for-Broadcom-STB-PCI.patch +Patch0022: 0022-config-Enable-support-for-the-XHCI-.patch +Patch0023: 0023-arm-rpi-Add-function-to-trigger-VL8.patch +Patch0024: 0024-usb-xhci-Load-Raspberry-Pi-4-VL805-.patch +Patch0025: 0025-config-Enable-USB-Keyboard-support-.patch # Patches: end BuildRequires: bc BuildRequires: bison ++++++ 0014-usb-xhci-Add-missing-cache-flush-in.patch ++++++ >From 96a515925eddcb28645391a0605710cfa79e7351 Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki <[email protected]> Date: Mon, 4 May 2020 14:45:14 +0200 Subject: [PATCH] usb: xhci: Add missing cache flush in the scratchpad array initialization In current code there is no cache flush after initializing the scratchpad buffer array with the scratchpad buffer pointers. This leads to a failure of the "slot enable" command on the rpi4 board (Broadcom STB PCIe controller + VL805 USB hub) - the very first TRB transfer on the command ring fails and there is a timeout while waiting for the command completion event. After adding the missing cache flush everything seems to be working as expected. Signed-off-by: Sylwester Nawrocki <[email protected]> Reviewed-by: Bin Meng <[email protected]> Reviewed-by: Nicolas Saenz Julienne <[email protected]> --- drivers/usb/host/xhci-mem.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c index 93450ee3b7..729bdc3c84 100644 --- a/drivers/usb/host/xhci-mem.c +++ b/drivers/usb/host/xhci-mem.c @@ -393,6 +393,9 @@ static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl) scratchpad->sp_array[i] = cpu_to_le64(ptr); } + xhci_flush_cache((uintptr_t)scratchpad->sp_array, + sizeof(u64) * num_sp); + return 0; fail_sp3: ++++++ 0015-usb-xhci-Use-only-32-bit-accesses-i.patch ++++++ >From 919357cfab0b8a07184b676b50c3a31582e3dcdc Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki <[email protected]> Date: Mon, 4 May 2020 14:45:15 +0200 Subject: [PATCH] usb: xhci: Use only 32-bit accesses in xhci_writeq/xhci_readq There might be hardware configurations where 64-bit data accesses to XHCI registers are not supported properly. This patch removes the readq/writeq so always two 32-bit accesses are used to read/write 64-bit XHCI registers, similarly as it is done in Linux kernel. This patch fixes operation of the XHCI controller on RPI4 Broadcom BCM2711 SoC based board, where the VL805 USB XHCI controller is connected to the PCIe Root Complex, which is attached to the system through the SCB bridge. Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely the 64-bit wide register accesses initiated by the CPU are not properly translated to a sequence of 32-bit PCIe accesses. xhci_readq(), for example, always returns same value in upper and lower 32-bits, e.g. 0xabcd1234abcd1234 instead of 0x00000000abcd1234. Cc: Sergey Temerkhanov <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]> Reviewed-by: Bin Meng <[email protected]> Reviewed-by: Nicolas Saenz Julienne <[email protected]> --- include/usb/xhci.h | 8 -------- 1 file changed, 8 deletions(-) diff --git a/include/usb/xhci.h b/include/usb/xhci.h index 6017504488..c16106a2fc 100644 --- a/include/usb/xhci.h +++ b/include/usb/xhci.h @@ -1111,28 +1111,20 @@ static inline void xhci_writel(uint32_t volatile *regs, const unsigned int val) */ static inline u64 xhci_readq(__le64 volatile *regs) { -#if BITS_PER_LONG == 64 - return readq(regs); -#else __u32 *ptr = (__u32 *)regs; u64 val_lo = readl(ptr); u64 val_hi = readl(ptr + 1); return val_lo + (val_hi << 32); -#endif } static inline void xhci_writeq(__le64 volatile *regs, const u64 val) { -#if BITS_PER_LONG == 64 - writeq(val, regs); -#else __u32 *ptr = (__u32 *)regs; u32 val_lo = lower_32_bits(val); /* FIXME */ u32 val_hi = upper_32_bits(val); writel(val_lo, ptr); writel(val_hi, ptr + 1); -#endif } int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr, ++++++ 0016-pci-Move-some-PCIe-register-offset-.patch ++++++ >From 18844a477d00a24fdeff913c4c277d53ee98094d Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki <[email protected]> Date: Mon, 4 May 2020 14:45:16 +0200 Subject: [PATCH] pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <[email protected]> Reviewed-by: Bin Meng <[email protected]> Reviewed-by: Nicolas Saenz Julienne <[email protected]> --- drivers/pci/pci-rcar-gen3.c | 8 -------- drivers/pci/pcie_intel_fpga.c | 3 --- include/pci.h | 13 +++++++++++-- 3 files changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c index 30eff67dca..393f1c9ca9 100644 --- a/drivers/pci/pci-rcar-gen3.c +++ b/drivers/pci/pci-rcar-gen3.c @@ -117,14 +117,6 @@ #define RCAR_PCI_MAX_RESOURCES 4 #define MAX_NR_INBOUND_MAPS 6 -#define PCI_EXP_FLAGS 2 /* Capabilities register */ -#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ -#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ -#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ -#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ -#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ -#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ - enum { RCAR_PCI_ACCESS_READ, RCAR_PCI_ACCESS_WRITE, diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c index 6a9f29c5c8..69363a077a 100644 --- a/drivers/pci/pcie_intel_fpga.c +++ b/drivers/pci/pcie_intel_fpga.c @@ -65,9 +65,6 @@ #define IS_ROOT_PORT(pcie, bdf) \ ((PCI_BUS(bdf) == pcie->first_busno) ? true : false) -#define PCI_EXP_LNKSTA 18 /* Link Status */ -#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ - /** * struct intel_fpga_pcie - Intel FPGA PCIe controller state * @bus: Pointer to the PCI bus diff --git a/include/pci.h b/include/pci.h index 174ddd4460..5bf91a43af 100644 --- a/include/pci.h +++ b/include/pci.h @@ -471,10 +471,19 @@ #define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */ /* PCI Express capabilities */ +#define PCI_EXP_FLAGS 2 /* Capabilities register */ +#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ +#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ #define PCI_EXP_DEVCAP 4 /* Device capabilities */ -#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ +#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ #define PCI_EXP_DEVCTL 8 /* Device Control */ -#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ +#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ +#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ +#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ +#define PCI_EXP_LNKSTA 18 /* Link Status */ +#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ +#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ +#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ /* Include the ID list */ ++++++ 0017-rpi4-shorten-a-mapping-for-the-DRAM.patch ++++++ >From 4db83106c1da071b0e4ee56675bdbf448f2961fc Mon Sep 17 00:00:00 2001 From: Marek Szyprowski <[email protected]> Date: Mon, 4 May 2020 14:45:17 +0200 Subject: [PATCH] rpi4: shorten a mapping for the DRAM Remove the overlap between DRAM and device's IO area. Signed-off-by: Marek Szyprowski <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]> Reviewed-by: Nicolas Saenz Julienne <[email protected]> --- arch/arm/mach-bcm283x/init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index 9966d6c833..42953561a7 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -38,7 +38,7 @@ static struct mm_region bcm2711_mem_map[] = { { .virt = 0x00000000UL, .phys = 0x00000000UL, - .size = 0xfe000000UL, + .size = 0xfc000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { ++++++ 0018-rpi4-add-a-mapping-for-the-PCIe-XHC.patch ++++++ >From c64da6a3c2950b925e95fb892e381ce89a869c8e Mon Sep 17 00:00:00 2001 From: Marek Szyprowski <[email protected]> Date: Mon, 4 May 2020 14:45:18 +0200 Subject: [PATCH] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 64bit) Create a non-cacheable mapping for the 0x600000000 physical memory region, where MMIO registers for the PCIe XHCI controller are instantiated by the PCIe bridge. Signed-off-by: Marek Szyprowski <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]> Reviewed-by: Nicolas Saenz Julienne <[email protected]> --- arch/arm/mach-bcm283x/init.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index 42953561a7..6a748da171 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -11,10 +11,15 @@ #include <dm/device.h> #include <fdt_support.h> +#define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS 0x600000000UL +#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE 0x800000UL + #ifdef CONFIG_ARM64 #include <asm/armv8/mmu.h> -static struct mm_region bcm283x_mem_map[] = { +#define MAX_MAP_MAX_ENTRIES (4) + +static struct mm_region bcm283x_mem_map[MAX_MAP_MAX_ENTRIES] = { { .virt = 0x00000000UL, .phys = 0x00000000UL, @@ -34,7 +39,7 @@ static struct mm_region bcm283x_mem_map[] = { } }; -static struct mm_region bcm2711_mem_map[] = { +static struct mm_region bcm2711_mem_map[MAX_MAP_MAX_ENTRIES] = { { .virt = 0x00000000UL, .phys = 0x00000000UL, @@ -48,6 +53,13 @@ static struct mm_region bcm2711_mem_map[] = { .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, + .phys = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, + .size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { /* List terminator */ 0, @@ -71,7 +83,7 @@ static void _rpi_update_mem_map(struct mm_region *pd) { int i; - for (i = 0; i < 2; i++) { + for (i = 0; i < MAX_MAP_MAX_ENTRIES; i++) { mem_map[i].virt = pd[i].virt; mem_map[i].phys = pd[i].phys; mem_map[i].size = pd[i].size; ++++++ 0019-linux-bitfield.h-Add-primitives-for.patch ++++++ >From 897da38f243dd23eeaa5e1103bbd9f7d47bc0f7f Mon Sep 17 00:00:00 2001 From: Nicolas Saenz Julienne <[email protected]> Date: Mon, 4 May 2020 14:45:20 +0200 Subject: [PATCH] linux/bitfield.h: Add primitives for manipulating bitfields both in host- and fixed-endian Imports Al Viro's original Linux commit 00b0c9b82663a, which contains an in depth explanation and two fixes from Johannes Berg: e7d4a95da86e0 "bitfield: fix *_encode_bits()", 37a3862e12382 "bitfield: add u8 helpers". Signed-off-by: Nicolas Saenz Julienne <[email protected]> [s.nawrocki: added empty lines between functions and macros] Signed-off-by: Sylwester Nawrocki <[email protected]> --- include/linux/bitfield.h | 50 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h index 8b9d6fff00..7acba4c524 100644 --- a/include/linux/bitfield.h +++ b/include/linux/bitfield.h @@ -103,4 +103,54 @@ (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ }) +extern void __compiletime_error("value doesn't fit into mask") +__field_overflow(void); +extern void __compiletime_error("bad bitfield mask") +__bad_mask(void); +static __always_inline u64 field_multiplier(u64 field) +{ + if ((field | (field - 1)) & ((field | (field - 1)) + 1)) + __bad_mask(); + return field & -field; +} +static __always_inline u64 field_mask(u64 field) +{ + return field / field_multiplier(field); +} + +#define ____MAKE_OP(type,base,to,from) \ +static __always_inline __##type type##_encode_bits(base v, base field) \ +{ \ + if (__builtin_constant_p(v) && (v & ~field_mask(field))) \ + __field_overflow(); \ + return to((v & field_mask(field)) * field_multiplier(field)); \ +} \ +static __always_inline __##type type##_replace_bits(__##type old, \ + base val, base field) \ +{ \ + return (old & ~to(field)) | type##_encode_bits(val, field); \ +} \ +static __always_inline void type##p_replace_bits(__##type *p, \ + base val, base field) \ +{ \ + *p = (*p & ~to(field)) | type##_encode_bits(val, field); \ +} \ +static __always_inline base type##_get_bits(__##type v, base field) \ +{ \ + return (from(v) & field)/field_multiplier(field); \ +} + +#define __MAKE_OP(size) \ + ____MAKE_OP(le##size,u##size,cpu_to_le##size,le##size##_to_cpu) \ + ____MAKE_OP(be##size,u##size,cpu_to_be##size,be##size##_to_cpu) \ + ____MAKE_OP(u##size,u##size,,) + +____MAKE_OP(u8,u8,,) +__MAKE_OP(16) +__MAKE_OP(32) +__MAKE_OP(64) + +#undef __MAKE_OP +#undef ____MAKE_OP + #endif ++++++ 0020-pci-Add-some-PCI-Express-capability.patch ++++++ >From 278f85de3e80c3240448bb133af65520294ec590 Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki <[email protected]> Date: Mon, 4 May 2020 14:45:21 +0200 Subject: [PATCH] pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <[email protected]> Reviewed-by: Bin Meng <[email protected]> Reviewed-by: Nicolas Saenz Julienne <[email protected]> --- include/pci.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/pci.h b/include/pci.h index 5bf91a43af..5307478b44 100644 --- a/include/pci.h +++ b/include/pci.h @@ -479,11 +479,17 @@ #define PCI_EXP_DEVCTL 8 /* Device Control */ #define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ +#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ +#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ #define PCI_EXP_LNKSTA 18 /* Link Status */ +#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ +#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ +#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ +#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ /* Include the ID list */ ++++++ 0021-pci-Add-driver-for-Broadcom-STB-PCI.patch ++++++ ++++ 646 lines (skipped) ++++++ 0022-config-Enable-support-for-the-XHCI-.patch ++++++ >From 7c75345077bc8f04a6a736b8e960df9799de20ac Mon Sep 17 00:00:00 2001 From: Marek Szyprowski <[email protected]> Date: Mon, 4 May 2020 14:45:23 +0200 Subject: [PATCH] config: Enable support for the XHCI controller on RPI4 board This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI and USB commands. To get it working one has to call the following commands: "pci enum; usb start;", thus such commands have been added to the default "preboot" environment variable. One has to update their environment if it is already configured to get this feature working out of the box. Signed-off-by: Marek Szyprowski <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]> --- configs/rpi_4_32b_defconfig | 9 +++++++++ configs/rpi_4_defconfig | 9 +++++++++ configs/rpi_arm64_defconfig | 8 +++++++- 3 files changed, 25 insertions(+), 1 deletion(-) diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig index 72cda5d949..1315f7449f 100644 --- a/configs/rpi_4_32b_defconfig +++ b/configs/rpi_4_32b_defconfig @@ -8,6 +8,8 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start;" CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set @@ -15,6 +17,8 @@ CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y CONFIG_OF_BOARD=y CONFIG_ENV_FAT_INTERFACE="mmc" @@ -28,6 +32,9 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y CONFIG_DM_ETH=y CONFIG_BCMGENET=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_BRCMSTB=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set @@ -40,6 +47,8 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y CONFIG_DM_VIDEO=y # CONFIG_VIDEO_BPP8 is not set # CONFIG_VIDEO_BPP16 is not set diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig index 6d148dab07..5051b8812f 100644 --- a/configs/rpi_4_defconfig +++ b/configs/rpi_4_defconfig @@ -8,6 +8,8 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start;" CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set @@ -15,6 +17,8 @@ CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y CONFIG_OF_BOARD=y CONFIG_ENV_FAT_INTERFACE="mmc" @@ -28,6 +32,9 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y CONFIG_DM_ETH=y CONFIG_BCMGENET=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_BRCMSTB=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set @@ -40,6 +47,8 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y CONFIG_DM_VIDEO=y # CONFIG_VIDEO_BPP8 is not set # CONFIG_VIDEO_BPP16 is not set diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig index fea86be8b0..f12d1e340c 100644 --- a/configs/rpi_arm64_defconfig +++ b/configs/rpi_arm64_defconfig @@ -7,13 +7,14 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y -CONFIG_PREBOOT="usb start" +CONFIG_PREBOOT="pci enum; usb start;" CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y CONFIG_OF_BOARD=y @@ -26,11 +27,16 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y CONFIG_DM_ETH=y CONFIG_BCMGENET=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_BRCMSTB=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y CONFIG_USB_DWC2=y CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y ++++++ 0023-arm-rpi-Add-function-to-trigger-VL8.patch ++++++ >From 3f74d0b9505c8718bfea156599e35ca260975780 Mon Sep 17 00:00:00 2001 From: Nicolas Saenz Julienne <[email protected]> Date: Tue, 5 May 2020 18:26:06 +0200 Subject: [PATCH] arm: rpi: Add function to trigger VL805's firmware load On the Raspberry Pi 4, after a PCI reset, VL805's (a xHCI chip) firmware may either be loaded directly from an EEPROM or, if not present, by the SoC's VideCore (the SoC's co-processor). Introduce the function that informs VideCore that VL805 may need its firmware loaded. Signed-off-by: Nicolas Saenz Julienne <[email protected]> --- arch/arm/mach-bcm283x/include/mach/mbox.h | 13 +++++++ arch/arm/mach-bcm283x/include/mach/msg.h | 7 ++++ arch/arm/mach-bcm283x/msg.c | 45 +++++++++++++++++++++++ 3 files changed, 65 insertions(+) diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h index 60e226ce1d..2ae2d3d97c 100644 --- a/arch/arm/mach-bcm283x/include/mach/mbox.h +++ b/arch/arm/mach-bcm283x/include/mach/mbox.h @@ -491,6 +491,19 @@ struct bcm2835_mbox_tag_set_palette { } body; }; +#define BCM2835_MBOX_TAG_NOTIFY_XHCI_RESET 0x00030058 + +struct bcm2835_mbox_tag_pci_dev_addr { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + struct { + u32 dev_addr; + } req; + struct { + } resp; + } body; +}; + /* * Pass a raw u32 message to the VC, and receive a raw u32 back. * diff --git a/arch/arm/mach-bcm283x/include/mach/msg.h b/arch/arm/mach-bcm283x/include/mach/msg.h index 4afb08631b..f5213dd0e0 100644 --- a/arch/arm/mach-bcm283x/include/mach/msg.h +++ b/arch/arm/mach-bcm283x/include/mach/msg.h @@ -48,4 +48,11 @@ int bcm2835_set_video_params(int *widthp, int *heightp, int depth_bpp, int pixel_order, int alpha_mode, ulong *fb_basep, ulong *fb_sizep, int *pitchp); +/** + * bcm2711_notify_vl805_reset() - get vl805's firmware loaded + * + * @return 0 if OK, -EIO on error + */ +int bcm2711_notify_vl805_reset(void); + #endif diff --git a/arch/arm/mach-bcm283x/msg.c b/arch/arm/mach-bcm283x/msg.c index 94b75283f8..f8ef531652 100644 --- a/arch/arm/mach-bcm283x/msg.c +++ b/arch/arm/mach-bcm283x/msg.c @@ -40,6 +40,12 @@ struct msg_setup { u32 end_tag; }; +struct msg_notify_vl805_reset { + struct bcm2835_mbox_hdr hdr; + struct bcm2835_mbox_tag_pci_dev_addr dev_addr; + u32 end_tag; +}; + int bcm2835_power_on_module(u32 module) { ALLOC_CACHE_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1); @@ -151,3 +157,42 @@ int bcm2835_set_video_params(int *widthp, int *heightp, int depth_bpp, return 0; } + +/* + * The Raspberry Pi 4 gets its USB functionality from VL805, a PCIe chip that + * implements xHCI. After a PCI reset, VL805's firmware may either be loaded + * directly from an EEPROM or, if not present, by the SoC's co-processor, + * VideoCore. RPi4's VideoCore OS contains both the non public firmware load + * logic and the VL805 firmware blob. This function triggers the aforementioned + * process. + */ +int bcm2711_notify_vl805_reset(void) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct msg_notify_vl805_reset, + msg_notify_vl805_reset, 1); + int ret; + + BCM2835_MBOX_INIT_HDR(msg_notify_vl805_reset); + BCM2835_MBOX_INIT_TAG(&msg_notify_vl805_reset->dev_addr, + NOTIFY_XHCI_RESET); + + /* + * The pci device address is expected like this: + * + * PCI_BUS << 20 | PCI_SLOT << 15 | PCI_FUNC << 12 + * + * But since RPi4's PCIe setup is hardwired, we know the address in + * advance. + */ + msg_notify_vl805_reset->dev_addr.body.req.dev_addr = 0x100000; + + ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, + &msg_notify_vl805_reset->hdr); + if (ret) { + printf("bcm2711: Faild to load vl805's firmware, %d\n", ret); + return -EIO; + } + + return 0; +} + ++++++ 0024-usb-xhci-Load-Raspberry-Pi-4-VL805-.patch ++++++ >From e5fa3a00fbbe9b19f0fa76e0c497e9d5acf940d6 Mon Sep 17 00:00:00 2001 From: Nicolas Saenz Julienne <[email protected]> Date: Tue, 5 May 2020 18:26:07 +0200 Subject: [PATCH] usb: xhci: Load Raspberry Pi 4 VL805's firmware When needed, RPi4's co-processor (called VideoCore) has to be instructed to load VL805's firmware (the chip providing xHCI support). VideCore's firmware expects the board's PCIe bus to be already configured in order for it to load the xHCI chip firmware. So we have to make sure this happens in between the PCIe configuration and xHCI startup. Introduce a callback in xhci_pci_probe() to run this platform specific routine. Signed-off-by: Nicolas Saenz Julienne <[email protected]> --- board/raspberrypi/rpi/rpi.c | 6 ++++++ drivers/usb/host/xhci-pci.c | 6 ++++++ include/usb/xhci.h | 3 +++ 3 files changed, 15 insertions(+) diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index e367ba3092..dcaf45fbf2 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -14,6 +14,7 @@ #include <lcd.h> #include <memalign.h> #include <mmc.h> +#include <usb/xhci.h> #include <asm/gpio.h> #include <asm/arch/mbox.h> #include <asm/arch/msg.h> @@ -494,3 +495,8 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } + +void xhci_pci_fixup(struct udevice *dev) +{ + bcm2711_notify_vl805_reset(); +} diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c index c1f60da541..1285dde1ef 100644 --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c @@ -11,6 +11,10 @@ #include <usb.h> #include <usb/xhci.h> +__weak void xhci_pci_fixup(struct udevice *dev) +{ +} + static void xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr, struct xhci_hcor **ret_hcor) { @@ -40,6 +44,8 @@ static int xhci_pci_probe(struct udevice *dev) struct xhci_hccr *hccr; struct xhci_hcor *hcor; + xhci_pci_fixup(dev); + xhci_pci_init(dev, &hccr, &hcor); return xhci_register(dev, hccr, hcor); diff --git a/include/usb/xhci.h b/include/usb/xhci.h index c16106a2fc..57feed7603 100644 --- a/include/usb/xhci.h +++ b/include/usb/xhci.h @@ -16,6 +16,7 @@ #ifndef HOST_XHCI_H_ #define HOST_XHCI_H_ +#include <usb.h> #include <asm/types.h> #include <asm/cache.h> #include <asm/io.h> @@ -1281,4 +1282,6 @@ extern struct dm_usb_ops xhci_usb_ops; struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev); +extern void xhci_pci_fixup(struct udevice *dev); + #endif /* HOST_XHCI_H_ */ ++++++ 0025-config-Enable-USB-Keyboard-support-.patch ++++++ >From 8ae0b68bf17266338e1b5a91cc987f8f2dcba1ab Mon Sep 17 00:00:00 2001 From: Nicolas Saenz Julienne <[email protected]> Date: Tue, 5 May 2020 16:51:29 +0200 Subject: [PATCH] config: Enable USB Keyboard support on RPi4 Supporting USB keyboards out of the box is both handy for development and production. Notably if u-boot is used to boot into GRUB. Signed-off-by: Nicolas Saenz Julienne <[email protected]> Reviewed-by: Sylwester Nawrocki <[email protected]> Reviewed-by: Bin Meng <[email protected]> --- configs/rpi_4_32b_defconfig | 1 + configs/rpi_4_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig index 1315f7449f..2c5539102e 100644 --- a/configs/rpi_4_32b_defconfig +++ b/configs/rpi_4_32b_defconfig @@ -49,6 +49,7 @@ CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI=y +CONFIG_USB_KEYBOARD=y CONFIG_DM_VIDEO=y # CONFIG_VIDEO_BPP8 is not set # CONFIG_VIDEO_BPP16 is not set diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig index 5051b8812f..6f34ae9fbd 100644 --- a/configs/rpi_4_defconfig +++ b/configs/rpi_4_defconfig @@ -49,6 +49,7 @@ CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI=y +CONFIG_USB_KEYBOARD=y CONFIG_DM_VIDEO=y # CONFIG_VIDEO_BPP8 is not set # CONFIG_VIDEO_BPP16 is not set
