Hello community, here is the log from the commit of package iverilog for openSUSE:Factory checked in at 2020-10-02 17:36:08 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/iverilog (Old) and /work/SRC/openSUSE:Factory/.iverilog.new.4249 (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "iverilog" Fri Oct 2 17:36:08 2020 rev:8 rq:838834 version:11.0 Changes: -------- --- /work/SRC/openSUSE:Factory/iverilog/iverilog.changes 2019-07-28 10:23:06.460567284 +0200 +++ /work/SRC/openSUSE:Factory/.iverilog.new.4249/iverilog.changes 2020-10-02 17:36:17.698702541 +0200 @@ -1,0 +2,10 @@ +Tue Sep 29 12:55:03 UTC 2020 - Stefan Brüns <[email protected]> + +- Update to version 11.0 + * No changelog available + * Remove obsolete patches: + + Fix-makefile-rules-for-header-files-generated-by-bison.patch + + fix-cfparse-include-order-causing-lto-type-mismatch.patch +- Spec cleanup + +------------------------------------------------------------------- Old: ---- Fix-makefile-rules-for-header-files-generated-by-bison.patch fix-cfparse-include-order-causing-lto-type-mismatch.patch verilog-10.2.tar.gz New: ---- verilog-11.0.tar.gz ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ iverilog.spec ++++++ --- /var/tmp/diff_new_pack.2oygZc/_old 2020-10-02 17:36:20.150704004 +0200 +++ /var/tmp/diff_new_pack.2oygZc/_new 2020-10-02 17:36:20.154704006 +0200 @@ -1,7 +1,7 @@ # # spec file for package iverilog # -# Copyright (c) 2019 SUSE LINUX GmbH, Nuernberg, Germany. +# Copyright (c) 2020 SUSE LLC # # All modifications and additions to the file contributed by third parties # remain the property of their copyright owners, unless otherwise agreed @@ -17,26 +17,22 @@ Name: iverilog -Version: 10.2 +Version: 11.0 Release: 0 -%define major_ver 10 +%define major_ver 11 Summary: Simulation and synthesis tool for IEEE-1364 License: GPL-2.0-or-later Group: Productivity/Scientific/Electronics -Url: http://iverilog.icarus.com/ +URL: http://iverilog.icarus.com/ Source: ftp://icarus.com/pub/eda/verilog/v%{major_ver}/verilog-%{version}.tar.gz -# PATCH-FIX-UPSTREAM https://github.com/steveicarus/iverilog/commit/5bb6c7f53a6ab5b44c282ba5b118927fd4f17e4f.patch -Patch0: Fix-makefile-rules-for-header-files-generated-by-bison.patch -# PATCH-FIX-UPSTREAM https://patch-diff.githubusercontent.com/raw/steveicarus/iverilog/pull/257.patch -Patch1: fix-cfparse-include-order-causing-lto-type-mismatch.patch BuildRequires: bison BuildRequires: fdupes BuildRequires: flex BuildRequires: gcc-c++ BuildRequires: gperf +BuildRequires: libbz2-devel BuildRequires: readline-devel BuildRequires: zlib-devel -BuildRoot: %{_tmppath}/%{name}-%{version}-build %description Icarus Verilog is a Verilog compiler that generates a variety of @@ -53,14 +49,10 @@ %prep %setup -q -n verilog-%{version} -%patch0 -p1 -%patch1 -p1 %build %configure -# Can not use make_build here, as the V=1 overwrites a Makefile variable -# https://github.com/steveicarus/iverilog/issues/256 -make %{_smp_mflags} +%make_build %install %make_install ++++++ verilog-10.2.tar.gz -> verilog-11.0.tar.gz ++++++ ++++ 61509 lines of diff (skipped)
