Hello community, here is the log from the commit of package cpuid for openSUSE:Factory checked in at 2020-10-08 13:14:34 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/cpuid (Old) and /work/SRC/openSUSE:Factory/.cpuid.new.4249 (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "cpuid" Thu Oct 8 13:14:34 2020 rev:11 rq:840201 version:20201006 Changes: -------- --- /work/SRC/openSUSE:Factory/cpuid/cpuid.changes 2020-04-29 20:53:23.169135833 +0200 +++ /work/SRC/openSUSE:Factory/.cpuid.new.4249/cpuid.changes 2020-10-08 13:14:42.631309668 +0200 @@ -1,0 +2,10 @@ +Thu Oct 8 08:19:24 UTC 2020 - Josef Möllers <[email protected]> + +- Update to 20201006: + Added "Sapphire Rapids", "Golden Cove", "Rocket Lake", "Cato", + 14nm "Zen", "Tiger Lake-U B0", "Elkhart Lake B0", "Alder Lake", + "Comet Lake", "Picasso A1", "Renoir A1", "Zhaoxin KaiXian KX-6000", + as well as some additional decoding of supported features. + [cpuid-20201006.src.tar.gz, jsc#sle-13189] + +------------------------------------------------------------------- Old: ---- cpuid-20200427.src.tar.gz New: ---- cpuid-20201006.src.tar.gz ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ cpuid.spec ++++++ --- /var/tmp/diff_new_pack.R5cZO3/_old 2020-10-08 13:14:43.195310179 +0200 +++ /var/tmp/diff_new_pack.R5cZO3/_new 2020-10-08 13:14:43.199310182 +0200 @@ -17,7 +17,7 @@ Name: cpuid -Version: 20200427 +Version: 20201006 Release: 0 Summary: x86 CPU identification tool License: GPL-2.0-or-later ++++++ cpuid-20200427.src.tar.gz -> cpuid-20201006.src.tar.gz ++++++ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20200427/ChangeLog new/cpuid-20201006/ChangeLog --- old/cpuid-20200427/ChangeLog 2020-04-27 14:10:31.000000000 +0200 +++ new/cpuid-20201006/ChangeLog 2020-10-06 14:39:53.000000000 +0200 @@ -1,3 +1,88 @@ +Tue Oct 6 2020 Todd Allen <[email protected]> + * Made new release. + +Tue Oct 6 2020 Todd Allen <[email protected]> + * cpuid.c: Added 6/eax enhanced hardware feedback interface. + * cpuid.c: Added 6/ecx number of enh hardware feedback classes. + * cpuid.c: Added 7/0/ecx KL: key locker. + * cpuid.c: Added 7/0/edx UINTR: user interrupts. + * cpuid.c: Added 7/0/edx AVX512_FP16: fp16 support. + * cpuid.c: Added 7/1/eax AVX-VNNI: AVX VNNI neural network instrs. + * cpuid.c: Added 7/1/eax zero-length MOVSB. + * cpuid.c: Added 7/1/eax fast short STOSB. + * cpuid.c: Added 7/1/eax fast short CMPSB, SCASB. + * cpuid.c: Added 7/1/eax HRESET: history reset support. + * cpuid.c: Added 0xa/ecx fixed counter support enumeration. + * cpuid.c: Added 0xd/0/eax IA32_XSS UINTR state. + * cpuid.c: Added 0xd/n UINTR feature. + * cpuid.c: Added 0x19 key locker features. + * cpuid.c: Added 0x20 HRESET features. + +Mon Oct 5 2020 Todd Allen <[email protected]> + * cpuid.c: Added (7,5),(2,6) AMD Cato (synth) decoding based on + instlatx64 example (possibly an engr sample). + +Sun Oct 4 2020 Todd Allen <[email protected]> + * cpuid.c: Corrected 6/edx size field to use minus-one notation. + * cpuid.c: Added 7/0/edx AMX flags. + * cpuid.c: Added 0xd XTILECFG & XTILEDATA features. + * cpuid.c: Added 0xd/1/eax XFD: extended feature disable supported flag. + * cpuid.c: Added 0xd/n/ecx XFD: faulting supported flag. + * cpuid.c: Added 0x18/0/edx: load-only TLB & store-only TLB encodings. + * cpuid.c: Added 0x1d leaf (Tile info) decoding. + * cpuid.c: Added 0x1e leaf (TMUL) decoding. + * cpuid.c: Added 0x1c leaf (architectural LBR) decoding. + * cpuid.c: Added 0xd LBR features. + +Sun Oct 4 2020 Todd Allen <[email protected]> + * cpuid.c: Added (synth) steppings for Comet Lake (0,6),(10,6) CPUs. + For the first time in a long time, Intel actually provided this in + the revision guide (615213)! + * cpuid.c: Corrected (synth) decoding for AMD (8,15),(2,0) Dali CPUs. + * cpuid.c: Added (synth) decoding for AMD Dali A1 stepping. + * cpuid.c: Added (synth) decoding for AMD Picasso A1 stepping. + * cpuid.c: Added (synth) decoding for AMD Renoir A1 stepping. + +Sat Oct 3 2020 Todd Allen <[email protected]> + * cpuid.c: Added 7/0/ecx PKS flag. + * cpuid.c: Added 7/0/edx SRBDS flag, from Linux kernel. + * cpuid.c: Added 7/0/edx LBR flag. + * cpuid.c: Added 0xd/0/eax IA322_XSS HWP state flag. + * cpuid.c: Added synth decoding for Rocket Lake. + * cpuid.c: Added synth decoding for Elkhart Lake B0. + * cpuid.c: Added synth decoding for Alder Lake [Golden Cove]. + * cpuid.c: Clarified synth decoding for (0,6),(8,10) Lakefield. + * cpuid.c: Added KVM interrupt-based page-ready APF event flag. + +Sat Aug 8 2020 Todd Allen <[email protected]> + * cpuid.c: Corrected 0x20000001/edx header. + * cpuid.c: Detect bogus 0x20000000 leaf values and cap the maximum + valid register for the 0x2xxxxxxx range to avoid absurdly long dumps + on old CPUs. + +Mon Aug 3 2020 Todd Allen <[email protected]> + * cpuid.c: Added bzero before cpuid instruction, in case the cpuid + instruction quietly fails. This mostly is paranoia, but I don't see + how this ever could cause harm. + +Mon Jun 8 2020 Todd Allen <[email protected]> + * cpuid.c: Added Tiger Lake-U B0 stepping, from coreboot. + * cpuid.c: Added AMD (8,15),(2,0) Picasso model synth & uarch decoding. + +Sun May 24 2020 Todd Allen <[email protected]> + * cpuid.c: Added Zhaoxin KX-6000 decoding that still claims the vendor + CentaurHauls. Later Zhaoxin CPUs were supposed to use their own + vendor, but instlat64x showed an example that still used the old one. + +Sat May 16 2020 Todd Allen <[email protected]> + * cpuid.c: Added better (synth) decoding for Intel Comet Lake-H/S + Core i*-10000 CPUs, based on instlatx64 example and listings in + ark.intel.com. + +Tue Apr 28 2020 Todd Allen <[email protected]> + * cpuid.c: Added 0x8000000a/edx INVLPGB/TLBSYNC hypervisor intercept + enable flag. + Mon Apr 27 2020 Todd Allen <[email protected]> * Made new release. diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20200427/FAMILY.NOTES new/cpuid-20201006/FAMILY.NOTES --- old/cpuid-20200427/FAMILY.NOTES 2020-04-24 18:23:47.000000000 +0200 +++ new/cpuid-20201006/FAMILY.NOTES 2020-10-04 19:22:11.000000000 +0200 @@ -46,7 +46,8 @@ 10000 Series : Sunny Cove : new architecture (Ice Lake) Comet Lake * optim of {Coffee, Whiskey} Lake (K,U) ----------------------------------------------------------------------------- - future : Willow Cove : optim of Sunny Cove (Tiger Lake) [summer 2020?] + 11000 ? : Willow Cove : optim of Sunny Cove (Tiger Lake) (10nm) [summer 2020?] + Rocket Lake : Willow Cove but with (14nm) ----------------------------------------------------------------------------- * = I'm not treating this as a distinct uarch, but just as a core within its @@ -68,27 +69,34 @@ Y = extremely lower power (even lower than U) S = special edition (>= 9000) or performance-optimized (<= 4000) + Xeon: + Grantley / R3 = Broadwell + Purley / P = Skylake + Purley / P = Cascade Lake + Whitley / P+ = Ice Lake + Eagle Stream = Sapphire Rapids (based on Sunny Cove?) [2021] + Intel Atom architectures: - Mobile phones Notebooks Servers PCs Embedded/Automotive Network - ------------------------------------------------------------------------------------------------------- - Bonnell Silverthorne Diamondville - Bonnell 2 Lincroft Pineview Tunnel Creek/Stellarton - Saltwell Medfield Cedarview Centerton - " Clover Trail - ------------------------------------------------------------------------------------------------------- - Silvermont Merrifield Bay Trail Avoton Bay Trail Bay Trail Rangeley - " Moorefield - " SoFIA - Airmont Cherry Trail Braswell - ------------------------------------------------------------------------------------------------------- - Goldmont Willow Trail* Denverton Apollo Lake Apollo Lake - Apollo Lake - Goldmont+ Gemini Lake - ------------------------------------------------------------------------------------------------------- - Tremont Elkhart Lake Skyhawk Lake/ - Jasper Lake - ------------------------------------------------------------------------------------------------------- + Mobile phones Notebooks Servers PCs Embedded/Automotive Network + ------------------------------------------------------------------------------------------------------------- + 2008 Bonnell Silverthorne Diamondville + Bonnell 2 Lincroft Pineview Tunnel Creek/Stellarton + 2011 Saltwell Medfield Cedarview Centerton + " Clover Trail + ------------------------------------------------------------------------------------------------------------- + 2013 Silvermont Merrifield Bay Trail Avoton Bay Trail Bay Trail Rangeley + " Moorefield + " SoFIA + 2015 Airmont Cherry Trail Braswell + ------------------------------------------------------------------------------------------------------------- + 2016 Goldmont Willow Trail* Denverton Apollo Lake Apollo Lake + Apollo Lake + 2017 Goldmont+ Gemini Lake + ------------------------------------------------------------------------------------------------------------- + 2020 Tremont Elkhart Lake Skyhawk Lake/ + Jasper Lake + ------------------------------------------------------------------------------------------------------------- Mobile phones: @@ -218,6 +226,7 @@ ----------------------------------------------------------------------------------------------------------------------------------- Zen Summit Ridge Raven Ridge Naples/Snowy Owl Great Horned Owl/Banded Kestrel Zen+ Pinnacle Ridge/Picasso/Colfax Picasso + Dali Dali Zen 2 Castle Peak Rome (update) Matisse Renoir Dali ---future-------------------------------------------------------------------------------------------------------------------------- diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20200427/FUTURE new/cpuid-20201006/FUTURE --- old/cpuid-20200427/FUTURE 2020-03-06 17:08:11.000000000 +0100 +++ new/cpuid-20201006/FUTURE 2020-10-06 14:38:06.000000000 +0200 @@ -12,7 +12,6 @@ Cannon Lake [Palm Cove] (0,6),(6,6) spec update. Ice Lake [Sunny Cove] (0,6),(6,10) spec update. Ice Lake [Sunny Cove] (0,6),(6,12) spec update. - Tiger Lake [Willow Cove] (0,6),(8,12) spec update. Tiger Lake [Willow Cove] (0,6),(8,13) spec update. Spring Hill (aka Ice Lake NPP-I) (0,6),(9,13) spec update. Comet Lake [Kaby Lake] (0,6),(10,5) spec update. @@ -31,12 +30,12 @@ Atom Puma 7 (0,6),(6,14) spec update. - Lakefield (Sunny Cove + 4x Tremont?): Sunny Cove & Tremont FMS? + Lakefield (Sunny Cove + 4x Tremont?): Sunny Cove & Tremont FMS? + Alder Lake (Golden Cove + Gracemont) [~2021] AMD: Add EPYC series numbers (e.g. EPYC 7000 = Rome) - Zen 2 revision guide. Zen 3 models (Vermeer: desktop, Milan: server, Genesis Peak: Threadripper) -------------------------------------------------------------------------------- @@ -53,6 +52,7 @@ Intel: Atom S12x9 (Briarwood) is based on Cedar Trail, but the Intel docs provide no CPUID identification values. And I can find no examples online. Does anyone know the CPUID family/model/steppings? + AMD: Cato (7,15),(2,6) (real or only engr samples?) AMD: Geneva (the Athlon II Neo counterpart of the Athlon II mobile Champlain, or the V-Series Champlain?) [not seen in any revision guides yet, though] diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20200427/Makefile new/cpuid-20201006/Makefile --- old/cpuid-20200427/Makefile 2020-04-27 14:09:46.000000000 +0200 +++ new/cpuid-20201006/Makefile 2020-10-06 13:30:06.000000000 +0200 @@ -8,7 +8,7 @@ INSTALL_STRIP=-s PACKAGE=cpuid -VERSION=20200427 +VERSION=20201006 RELEASE=1 PROG=$(PACKAGE) diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20200427/cpuid.c new/cpuid-20201006/cpuid.c --- old/cpuid-20200427/cpuid.c 2020-04-22 14:57:11.000000000 +0200 +++ new/cpuid-20201006/cpuid.c 2020-10-06 14:40:46.000000000 +0200 @@ -34,8 +34,8 @@ // The "hook" to find these generally is an X86_FEATURE_* flag in: // arch/x86/include/asm/cpufeatures.h // For (synth) and (uarch synth) decoding, it often indicates -// family/model/stepping value which are documented nowhere else. These usually -// can be found in: +// family/model/stepping values which are documented nowhere else. These +// usually can be found in: // arch/x86/include/asm/intel-family.h // Coreboot* indicates (synth) or (uarch synth) decoding for which I have seen @@ -2086,11 +2086,14 @@ FM ( 0, 6, 7,14, *u = "Sunny Cove", *f = "Sunny Cove", *p = "10nm"); FM ( 0, 6, 8, 5, *u = "Knights Mill", *ciu = TRUE, *p = "14nm"); // no spec update; only MSR_CPUID_table* so far FM ( 0, 6, 8, 6, *u = "Tremont", *p = "10nm"); // LX* - FM ( 0, 6, 8,10, *u = "Tremont", *p = "10nm"); // no spec update; only geekbench.com example + FM ( 0, 6, 8,10, *u = "Tremont", *p = "10nm"); // no spec update; LX* FM ( 0, 6, 8,12, *u = "Willow Cove", *f = "Sunny Cove", *p = "10nm"); // found only on en.wikichip.org FM ( 0, 6, 8,13, *u = "Willow Cove", *f = "Sunny Cove", *p = "10nm"); // LX* FM ( 0, 6, 8,14, *u = "Kaby Lake", *f = "Skylake", *p = "14nm"); + FM ( 0, 6, 8,15, *u = "Sapphire Rapids", *f = "Sunny Cove", *p = "10nm"); // LX* FM ( 0, 6, 9, 6, *u = "Tremont", *p = "10nm"); // LX* + FM ( 0, 6, 9, 7, *u = "Golden Cove", *p = "10nm"); // LX* + FM ( 0, 6, 9,10, *u = "Golden Cove", *p = "10nm"); // Coreboot* FM ( 0, 6, 9,12, *u = "Tremont", *p = "10nm"); // LX* FM ( 0, 6, 9,13, *u = "Sunny Cove", *f = "Sunny Cove", *p = "10nm"); // LX* FMS ( 0, 6, 9,14, 9, *u = "Kaby Lake", *f = "Skylake", *p = "14nm"); @@ -2101,6 +2104,7 @@ FM ( 0, 6, 9,14, *u = "Kaby Lake / Coffee Lake", *f = "Skylake", *p = "14nm"); FM ( 0, 6, 10, 5, *u = "Kaby Lake", *f = "Skylake", *p = "14nm"); // LX* FM ( 0, 6, 10, 6, *u = "Kaby Lake", *f = "Skylake", *p = "14nm"); // no spec update; only instlatx64 example + FM ( 0, 6, 10, 7, *u = "Rocket Lake", *f = "Sunny Cove", *p = "14nm"); // LX* F ( 0, 7, *u = "Itanium"); FM ( 0,11, 0, 0, *u = "Knights Ferry", *ciu = TRUE, *f = "K1OM", *p = "45nm"); // found only on en.wikichip.org FM ( 0,11, 0, 1, *u = "Knights Corner", *ciu = TRUE, *f = "K1OM", *p = "22nm"); @@ -2204,14 +2208,16 @@ FM ( 6,15, 6, 5, *u = "Excavator", *p = "28nm"); // undocumented, but sample from Alexandros Couloumbis FM ( 6,15, 7, 0, *u = "Excavator", *p = "28nm"); FM ( 7,15, 0, 0, *u = "Jaguar", *p = "28nm"); + FM ( 7,15, 2, 6, *u = "Cato", *p = "28nm"); // only instlatx64 example; engr sample? FM ( 7,15, 3, 0, *u = "Puma 2014", *p = "28nm"); FM ( 8,15, 0, 0, *u = "Zen", *p = "14nm"); // instlatx64 engr sample FM ( 8,15, 0, 1, *u = "Zen", *p = "14nm"); FM ( 8,15, 0, 8, *u = "Zen+", *p = "12nm"); FM ( 8,15, 1, 1, *u = "Zen", *p = "14nm"); // found only on en.wikichip.org & instlatx64 examples - FM ( 8,15, 1, 8, *u = "Zen+", *p = "12nm"); // found only on en.wikichip.org + FM ( 8,15, 1, 8, *u = "Zen+", *p = "12nm"); + FM ( 8,15, 2, 0, *u = "Zen", *p = "14nm"); FM ( 8,15, 3, 1, *u = "Zen 2", *p = "7nm"); // found only on en.wikichip.org - FM ( 8,15, 6, 0, *u = "Zen 2", *p = "7nm"); // undocumented, geekbench.com example + FM ( 8,15, 6, 0, *u = "Zen 2", *p = "7nm"); FM ( 8,15, 7, 1, *u = "Zen 2", *p = "7nm"); // undocumented, but samples from Steven Noonan F (10,15, *u = "Zen 3", *p = "7nm"); // undocumented, LX* DEFAULT ((void)NULL); @@ -3283,9 +3289,10 @@ // MRG* 2018-03-06 mentions stepping 0, but doesn't specify which stepping name it is. FM ( 0, 6, 8, 5, "Intel Xeon Phi (Knights Mill)"); FM ( 0, 6, 8, 6, "Intel Atom (Elkhart Lake)"); - FM ( 0, 6, 8,10, "Intel Atom"); // no spec update; geekbench.com example - // Coreboot* provides stepping. + FM ( 0, 6, 8,10, "Intel Atom (Lakefield)"); // no spec update; LX* + // Coreboot* provides steppings. FMS ( 0, 6, 8,12, 0, "Intel Core (Tiger Lake-U A0)"); + FMS ( 0, 6, 8,12, 1, "Intel Core (Tiger Lake-U B0)"); FM ( 0, 6, 8,12, "Intel Core (Tiger Lake-U)"); FM ( 0, 6, 8,13, "Intel Core (Tiger Lake)"); // LX* // Intel docs (334663) omit the stepping numbers for (0,6),(8,14) @@ -3311,10 +3318,18 @@ FMSQ( 0, 6, 8,14, 12, dC, "Intel Celeron 5000U (Comet Lake-U V1)"); // MRG* 2019-08-31 pinned down stepping FMS ( 0, 6, 8,14, 12, "Intel (unknown type) (Whiskey Lake-U V0 / Comet Lake-U V1)"); FM ( 0, 6, 8,14, "Intel Core (unknown type) (Kaby Lake / Amber Lake-Y / Whiskey Lake-U / Comet Lake-U)"); + FM ( 0, 6, 8,15, "Intel Xeon (unknown type) (Sapphire Rapids)"); // LX* // LX*. Coreboot* provides stepping. FMS ( 0, 6, 9, 6, 0, "Intel Atom (Elkhart Lake A0)"); + FMS ( 0, 6, 9, 6, 1, "Intel Atom (Elkhart Lake B0)"); FM ( 0, 6, 9, 6, "Intel Atom (Elkhart Lake)"); // LX*. Coreboot* provides stepping. + FMS ( 0, 6, 9, 7, 0, "Intel Atom (Alder Lake-S A0)"); + FM ( 0, 6, 9, 7, "Intel Atom (Alder Lake-S)"); + // Coreboot*. Coreboot* provides stepping. + FMS ( 0, 6, 9,10, 0, "Intel Atom (Alder Lake-P A0)"); + FM ( 0, 6, 9,10, "Intel Atom (Alder Lake-P)"); + // LX*. Coreboot* provides stepping. FMS ( 0, 6, 9,12, 0, "Intel Atom (Jasper Lake A0)"); FM ( 0, 6, 9,12, "Intel Atom (Jasper Lake)"); FM ( 0, 6, 9,13, "Intel NNP I-1000 (Spring Hill)"); // LX* @@ -3336,19 +3351,35 @@ FMSQ( 0, 6, 9,14, 13, d1, "Intel CC150 (Coffee Lake R0)"); // no docs; only instlatx64 example FMSQ( 0, 6, 9,14, 13, dc, "Intel Core i*-9000 H Line (Coffee Lake R0)"); FMSQ( 0, 6, 9,14, 13, sX, "Intel Xeon E-2200 (Coffee Lake R0)"); // no docs on stepping; only MRG 2019-11-13 - FM ( 0, 6, 9,14, "Intel Core (unknown type) (Kaby Lake / Coffee Lake)"); + FM ( 0, 6, 9,14, "Intel (unknown type) (Kaby Lake / Coffee Lake)"); // LX*. Coreboot* provides more detail & steppings - // (615213) mentions the (0,6),(10,5),2 stepping, but does not provide its name. - FMS ( 0, 6, 10, 5, 0, "Intel (unknown model) (Comet Lake-H/S G0)"); - FMS ( 0, 6, 10, 5, 1, "Intel (unknown model) (Comet Lake-H/S P0)"); - FMS ( 0, 6, 10, 5, 3, "Intel (unknown model) (Comet Lake-H/S G1)"); - FMS ( 0, 6, 10, 5, 4, "Intel (unknown model) (Comet Lake-H/S Q0/P1)"); - FM ( 0, 6, 10, 5, "Intel (unknown model) (Comet Lake-H/S)"); + // (615213) mentions the (0,6),(10,5),2 and (0,6),(10,5),5 steppings, but + // does not provide their names. + // en.wikichip.org provides more details on stepping names. + FMSQ( 0, 6, 10, 5, 0, dc, "Intel Core i*-10000 (Comet Lake-H/S G0)"); + FMS ( 0, 6, 10, 5, 0, "Intel (unknown type) (Comet Lake-H/S G0)"); + FMSQ( 0, 6, 10, 5, 1, dc, "Intel Core i*-10000 (Comet Lake-H/S P0)"); + FMS ( 0, 6, 10, 5, 1, "Intel (unknown type) (Comet Lake-H/S P0)"); + FMSQ( 0, 6, 10, 5, 2, dc, "Intel Core i*-10000 (Comet Lake-H/S R1)"); + FMS ( 0, 6, 10, 5, 2, "Intel (unknown type) (Comet Lake-H/S R1)"); + FMSQ( 0, 6, 10, 5, 3, dc, "Intel Core i*-10000 (Comet Lake-H/S G1)"); + FMS ( 0, 6, 10, 5, 3, "Intel (unknown type) (Comet Lake-H/S G1)"); + FMSQ( 0, 6, 10, 5, 4, dc, "Intel Core i*-10000 (Comet Lake-H/S P1)"); + FMS ( 0, 6, 10, 5, 4, "Intel (unknown type) (Comet Lake-H/S P1)"); + FMSQ( 0, 6, 10, 5, 5, dc, "Intel Core i*-10000 (Comet Lake-H/S Q0)"); + FMS ( 0, 6, 10, 5, 5, "Intel (unknown type) (Comet Lake-H/S Q0)"); + FMQ ( 0, 6, 10, 5, dc, "Intel Core i*-10000 (Comet Lake-H/S)"); + FM ( 0, 6, 10, 5, "Intel (unknown type) (Comet Lake-H/S)"); + // (615213) provides steppings. // MRG* 2019-11-13 & instlatx64 example // Coreboot* provides steppings. FMS ( 0, 6, 10, 6, 0, "Intel Core i*-10000 (Comet Lake-U A0)"); - FMS ( 0, 6, 10, 6, 1, "Intel Core i*-10000 (Comet Lake-U K0/S0)"); - FM ( 0, 6, 10, 6, "Intel Core i*-10000 (Comet Lake-U)"); + FMS ( 0, 6, 10, 6, 1, "Intel Core i*-10000 (Comet Lake-U K0/K1/S0)"); + FMS ( 0, 6, 10, 6, 2, "Intel Core i*-10000 (Comet Lake-H R1)"); + FMS ( 0, 6, 10, 6, 3, "Intel Core i*-10000 (Comet Lake-S G1)"); + FMS ( 0, 6, 10, 6, 5, "Intel Core i*-10000 (Comet Lake-S Q0)"); + FM ( 0, 6, 10, 6, "Intel Core i*-10000 (Comet Lake)"); + FM ( 0, 6, 10, 7, "Intel (unknown type) (Rocket Lake)"); FQ ( 0, 6, sX, "Intel Xeon (unknown model)"); FQ ( 0, 6, se, "Intel Xeon (unknown model)"); FQ ( 0, 6, MC, "Intel Mobile Celeron (unknown model)"); @@ -4195,6 +4226,7 @@ FMQ ( 7,15, 0, 0, Sg, "AMD G-Series (Kabini)"); FMQ ( 7,15, 0, 0, sO, "AMD Opteron X1100/X2100 Series (Kyoto)"); FM ( 7,15, 0, 0, "AMD (unknown type) (Kabini/Temash/Kyoto)"); + FM ( 7,15, 2, 6, "AMD (unknown type) (Cato)"); // undocumented; instlatx64 sample; engr sample? // sandpile.org mentions (7,15),(0,4) Jaguar-esque "BV" cores // (with stepping 1 = A1), but I have no idea of any such code name. // The AMD docs (53072) omit the CPUID entirely. But if this sticks to the @@ -4240,7 +4272,10 @@ FMQ ( 8,15, 1, 1, ER, "AMD Ryzen Embedded (Great Horned Owl/Banded Kestrel)"); // only instlatx64 example FMQ ( 8,15, 1, 1, AR, "AMD Ryzen (Raven Ridge)"); // found only on en.wikichip.org & instlatx64 examples FM ( 8,15, 1, 1, "AMD Ryzen (unknown type) (Raven Ridge/Snowy Owl/Great Horned Owl/Banded Kestrel)"); // found only on en.wikichip.org & instlatx64 examples - FM ( 8,15, 1, 8, "AMD Ryzen (Picasso)"); // found only on en.wikichip.org + FMS ( 8,15, 1, 8, 1, "AMD Ryzen (Picasso A1)"); + FM ( 8,15, 1, 8, "AMD Ryzen (Picasso)"); + FMS ( 8,15, 2, 0, 1, "AMD Ryzen (Dali A1)"); + FM ( 8,15, 2, 0, "AMD Ryzen (Dali)"); FMSQ( 8,15, 3, 1, 0, dR, "AMD Ryzen (Castle Peak B0)"); FMQ ( 8,15, 3, 1, dR, "AMD Ryzen (Castle Peak)"); FMSQ( 8,15, 3, 1, 0, sE, "AMD EPYC (Rome B0)"); @@ -4248,7 +4283,8 @@ FMS ( 8,15, 3, 1, 0, "AMD Ryzen (Castle Peak B0) / EPYC (Rome B0)"); FM ( 8,15, 3, 1, "AMD Ryzen (Castle Peak) / EPYC (Rome)"); FM ( 8,15, 5, 0, "AMD DG02SRTBP4MFA (Fenghuang 15FF)"); // internal model, only instlatx64 example - FM ( 8,15, 6, 0, "AMD Ryzen (Renoir)"); // undocumented, instlatx64 examples (with stepping 1) + FMS ( 8,15, 6, 0, 1, "AMD Ryzen (Renoir A1)"); + FM ( 8,15, 6, 0, "AMD Ryzen (Renoir)"); FMS ( 8,15, 7, 1, 0, "AMD Ryzen (Matisse B0)"); // undocumented, but samples from Steven Noonan FM ( 8,15, 7, 1, "AMD Ryzen (Matisse)"); // undocumented, but samples from Steven Noonan F ( 8,15, "AMD (unknown model)"); @@ -4354,6 +4390,7 @@ FM (0, 6, 0,15, "VIA Nano / Eden (unknown type) (Isaiah)"); F (0, 6, "VIA C3 / C3-M / C7 / C7-M / Eden / Eden ESP 7000/8000/10000 / Nano (unknown model)"); FM (0, 7, 0,11, "Zhaoxin KaiXian KX-5000 / Kaisheng KH-20000 (WuDaoKou)"); // geekbench.com example + FMQ (0, 7, 3,11, vZ, "Zhaoxin KaiXian KX-6000 / Kaisheng KH-30000 (LuJiaZui)"); // instlatx64 example with CentaurHauls vendor! DEFAULT ("unknown"); return result; @@ -5601,8 +5638,9 @@ { "HWP PECI override" , 16, 16, bools }, { "flexible HWP" , 17, 17, bools }, { "IA32_HWP_REQUEST MSR fast access mode" , 18, 18, bools }, - { "HW_FEEDBACK" , 19, 19, bools }, + { "HW_FEEDBACK MSRs supported" , 19, 19, bools }, { "ignoring idle logical processor HWP req" , 20, 20, bools }, + { "enhanced hardware feedback interface" , 23, 23, bools }, }; print_names(value, names, LENGTH(names), @@ -5627,6 +5665,7 @@ = { { "hardware coordination feedback" , 0, 0, bools }, { "ACNT2 available" , 1, 1, bools }, { "performance-energy bias capability" , 3, 3, bools }, + { "number of enh hardware feedback classes" , 8, 11, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), @@ -5639,7 +5678,7 @@ static named_item names[] = { { "performance capability reporting" , 0, 0, bools }, { "energy efficiency capability reporting" , 1, 1, bools }, - { "size of feedback struct (4KB pages)" , 8, 11, NIL_IMAGES }, + { "size of feedback struct (4KB pages)" , 8, 11, MINUS1_IMAGES }, { "index of CPU's row in feedback struct" , 16, 31, NIL_IMAGES }, }; @@ -5711,11 +5750,13 @@ { "5-level paging" , 16, 16, bools }, { "BNDLDX/BNDSTX MAWAU value in 64-bit mode", 17, 21, NIL_IMAGES }, { "RDPID: read processor D supported" , 22, 22, bools }, + { "KL: key locker" , 23, 23, bools }, { "CLDEMOTE supports cache line demote" , 25, 25, bools }, { "MOVDIRI instruction" , 27, 27, bools }, { "MOVDIR64B instruction" , 28, 28, bools }, { "ENQCMD instruction" , 29, 29, bools }, { "SGX_LC: SGX launch config supported" , 30, 30, bools }, + { "PKS: supervisor protection keys" , 31, 31, bools }, }; print_names(value, names, LENGTH(names), @@ -5729,13 +5770,20 @@ = { { "AVX512_4VNNIW: neural network instrs" , 2, 2, bools }, { "AVX512_4FMAPS: multiply acc single prec" , 3, 3, bools }, { "fast short REP MOV" , 4, 4, bools }, + { "UINTR: user interrupts" , 5, 5, bools }, { "AVX512_VP2INTERSECT: intersect mask regs", 8, 8, bools }, - { "VERW md-clear microcode support" , 10, 10, bools }, // Xen*/Qemu* - { "SERIALIZE" , 14, 14, bools }, + { "SRBDS mitigation MSR available" , 9, 9, bools }, // LX* + { "VERW MD_CLEAR microcode support" , 10, 10, bools }, + { "SERIALIZE instruction" , 14, 14, bools }, { "hybrid part" , 15, 15, bools }, { "TSXLDTRK: TSX suspend load addr tracking", 16, 16, bools }, { "PCONFIG instruction" , 18, 18, bools }, + { "LBR: architectural last branch records" , 19, 19, bools }, { "CET_IBT: CET indirect branch tracking" , 20, 20, bools }, + { "AMX-BF16: tile bfloat16 support" , 22, 22, bools }, + { "AVX512_FP16: fp16 support" , 23, 23, bools }, + { "AMX-TILE: tile architecture support" , 24, 24, bools }, + { "AMX-INT8: tile 8-bit integer support" , 25, 25, bools }, { "IBRS/IBPB: indirect branch restrictions" , 26, 26, bools }, { "STIBP: 1 thr indirect branch predictor" , 27, 27, bools }, { "L1D_FLUSH: IA32_FLUSH_CMD MSR" , 28, 28, bools }, @@ -5751,7 +5799,12 @@ print_7_1_eax(unsigned int value) { static named_item names[] - = { { "AVX512_BF16: bfloat16 instructions" , 5, 5, bools }, + = { { "AVX-VNNI: AVX VNNI neural network instrs", 4, 4, bools }, + { "AVX512_BF16: bfloat16 instructions" , 5, 5, bools }, + { "zero-length MOVSB" , 10, 10, bools }, + { "fast short STOSB" , 11, 11, bools }, + { "fast short CMPSB, SCASB" , 12, 12, bools }, + { "HRESET: history reset support" , 22, 22, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); @@ -5767,9 +5820,8 @@ { "length of EBX bit vector" , 24, 31, NIL_IMAGES }, }; - printf(" Architecture Performance Monitoring Features (0xa/eax):\n"); print_names(value, names, LENGTH(names), - /* max_len => */ 0); + /* max_len => */ 40); } static void @@ -5785,9 +5837,19 @@ { "branch mispred retired event not avail" , 6, 6, bools }, }; - printf(" Architecture Performance Monitoring Features (0xa/ebx):\n"); print_names(value, names, LENGTH(names), - /* max_len => */ 0); + /* max_len => */ 40); +} + +static void +print_a_ecx(unsigned int value) +{ + unsigned int bit; + for (bit = 0; bit < sizeof(value)*8; bit++) { + unsigned int field = BIT_EXTRACT_LE(value, bit, bit+1); + printf(" fixed counter %2u supported = %s\n", + bit, bools[field]); + } } static void @@ -5799,9 +5861,8 @@ { "anythread deprecation" , 15, 15, bools }, }; - printf(" Architecture Performance Monitoring Features (0xa/edx):\n"); print_names(value, names, LENGTH(names), - /* max_len => */ 0); + /* max_len => */ 40); } static void @@ -5856,7 +5917,6 @@ ** which of the bits are actually supported by the hardware, and is described ** better in 13.2: Enumeration of CPU Support for XSAVE Instructions and ** XSAVE-Supported Features. - // This is invariant across subleaves, so print it only once ** ** These align with the supported features[] in print_d_n() for values > 1. */ @@ -5874,6 +5934,11 @@ { " XCR0 supported: CET_U state" , 11, 11, bools }, { " XCR0 supported: CET_S state" , 12, 12, bools }, { " IA32_XSS supported: HDC state" , 13, 13, bools }, + { " IA32_XSS supported: UINTR state" , 14, 14, bools }, + { " LBR supported" , 15, 15, bools }, + { " IA32_XSS supported: HWP state" , 16, 16, bools }, + { " XTILECFG supported" , 17, 17, bools }, + { " XTILEDATA supported" , 18, 18, bools }, }; print_names(value, names, LENGTH(names), @@ -5888,6 +5953,7 @@ { "XSAVEC instruction" , 1, 1, bools }, { "XGETBV instruction" , 2, 2, bools }, { "XSAVES/XRSTORS instructions" , 3, 3, bools }, + { "XFD: extended feature disable supported" , 4, 4, bools }, }; print_names(value, names, LENGTH(names), @@ -5903,6 +5969,7 @@ static named_item names[] = { { "supported in IA32_XSS or XCR0" , 0, 0, which }, { "64-byte alignment in compacted XSAVE" , 1, 1, bools }, + { "XFD faulting supported" , 2, 2, bools }, }; print_names(value, names, LENGTH(names), @@ -5936,11 +6003,11 @@ /* 11 => */ "CET_U state", /* 12 => */ "CET_S state", /* 13 => */ "HDC", - /* 14 => */ "unknown", - /* 15 => */ "unknown", - /* 16 => */ "unknown", - /* 17 => */ "unknown", - /* 18 => */ "unknown", + /* 14 => */ "UINTR", + /* 15 => */ "LBR", + /* 16 => */ "HWP state", + /* 17 => */ "XTILECFG", + /* 18 => */ "XTILEDATA", /* 19 => */ "unknown", /* 20 => */ "unknown", /* 21 => */ "unknown", @@ -6297,10 +6364,12 @@ static void print_18_n_edx(unsigned int value) { - static ccstring tlbs[1<<5] = { /* 00000b => */ "invalid (0)", - /* 00001b => */ "data TLB", + static ccstring tlbs[1<<5] = { /* 00000b => */ "invalid (0)", + /* 00001b => */ "data TLB", /* 00010b => */ "instruction TLB", - /* 00011b => */ "unified TLB", }; + /* 00011b => */ "unified TLB", + /* 00100b => */ "load-only TLB", + /* 00101b => */ "store-only TLB" }; static named_item names[] = { { "translation cache type" , 0, 4, tlbs }, @@ -6314,6 +6383,44 @@ } static void +print_19_eax(unsigned int value) +{ + static named_item names[] + = { { "CPL0-only restriction supported" , 0, 0, bools }, + { "no-encrypt restriction supported" , 1, 1, bools }, + { "no-decrypt restriction supported" , 2, 2, bools }, + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 32); +} + +static void +print_19_ebx(unsigned int value) +{ + static named_item names[] + = { { "AESKLE: AES instructions" , 0, 0, bools }, + { "AES wide instructions" , 2, 2, bools }, + { "MSRs & IWKEY backups" , 4, 4, bools }, + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 32); +} + +static void +print_19_ecx(unsigned int value) +{ + static named_item names[] + = { { "LOADIWKEY NoBackup parameter" , 0, 0, bools }, + { "IWKEY randomization supported" , 1, 1, bools }, + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 32); +} + +static void print_1a_0_eax(unsigned int value) { static ccstring coretypes[1<<8] = { /* 00h-0fh => */ NULL, NULL, NULL, NULL, @@ -6359,6 +6466,116 @@ } static void +print_1c_eax(unsigned int value) +{ + static ccstring ipvs[1<<1] = { /* 0 => */ "EIP (0)", + /* 1 => */ "LIP (1)" }; + + static named_item names[] + = { { "IA32_LBR_DEPTH.DEPTH 8 supported" , 0, 0, bools }, + { "IA32_LBR_DEPTH.DEPTH 16 supported" , 1, 1, bools }, + { "IA32_LBR_DEPTH.DEPTH 24 supported" , 2, 2, bools }, + { "IA32_LBR_DEPTH.DEPTH 32 supported" , 3, 3, bools }, + { "IA32_LBR_DEPTH.DEPTH 40 supported" , 4, 4, bools }, + { "IA32_LBR_DEPTH.DEPTH 48 supported" , 5, 5, bools }, + { "IA32_LBR_DEPTH.DEPTH 56 supported" , 6, 6, bools }, + { "IA32_LBR_DEPTH.DEPTH 64 supported" , 7, 7, bools }, + { "deep C-state reset supported" , 30, 30, bools }, + { "LBR IP values contain" , 31, 31, ipvs }, + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 33); +} + +static void +print_1c_ebx(unsigned int value) +{ + static named_item names[] + = { { "CPL filtering supported" , 0, 0, bools }, + { "branch filtering supported" , 1, 1, bools }, + { "call-stack mode supported" , 2, 2, bools }, + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 33); +} + +static void +print_1c_ecx(unsigned int value) +{ + static named_item names[] + = { { "mispredict bit supported" , 0, 0, bools }, + { "timed LBRs supported" , 1, 1, bools }, + { "branch type field supported" , 2, 2, bools }, + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 33); +} + +static void +print_1d_n_eax(unsigned int value) +{ + static named_item names[] + = { { "total_tile_bytes" , 0, 15, NIL_IMAGES }, + { "bytes_per_tile" , 16, 31, NIL_IMAGES }, + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 16); +} + +static void +print_1d_n_ebx(unsigned int value) +{ + static named_item names[] + = { { "bytes_per_row" , 0, 15, NIL_IMAGES }, + { "max_names" , 16, 31, NIL_IMAGES }, + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 16); +} + +static void +print_1d_n_ecx(unsigned int value) +{ + static named_item names[] + = { { "max_rows" , 0, 15, NIL_IMAGES }, + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 16); +} + +static void +print_1e_ebx(unsigned int value) +{ + static named_item names[] + = { { "tmul_maxk" , 0, 7, NIL_IMAGES }, + { "tmul_maxn" , 8, 23, NIL_IMAGES }, + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 0); +} + +static void +print_20_ebx(unsigned int value) +{ + /* + ** The meanings of the bits correlate with the IA32_HRESET_ENABLE MSR bits. + */ + static named_item names[] + = { { "HRESET supported: EHFI history" , 0, 0, bools }, + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 0); +} + +static void print_20000001_edx(unsigned int value) { // I found a vague reference to this leaf in Intel Xeon Phi Coprocessor @@ -6370,7 +6587,7 @@ = { { "k1om" , 0, 0, bools }, }; - printf(" hypervisor features (0x40000001/eax):\n"); + printf(" Xeon Phi graphics function features (0x20000001/edx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } @@ -6392,6 +6609,7 @@ { "guest send IPI optimization enabled" , 11, 11, bools }, { "host HLT poll disable at MSR 0x4b564d05" , 12, 12, bools }, { "guest sched yield optimization enabled" , 13, 13, bools }, + { "guest uses intrs for page ready APF evs" , 14, 14, bools }, { "stable: no guest per-cpu warps expected" , 24, 24, bools }, }; @@ -7203,7 +7421,8 @@ NULL, "AM4 (2)" }; use_pkg_type = pkg_type; - } else if (__M(val_1_eax) == _XM(1) + _M(8)) { + } else if (__M(val_1_eax) == _XM(1) + _M(8) + || __M(val_1_eax) == _XM(2) + _M(0)) { static ccstring pkg_type[1<<4] = { "FP5 (0)", NULL, "AM4 (2)" }; @@ -7507,7 +7726,7 @@ print_80000008_edx(unsigned int value) { static named_item names[] - = { { "RDPRU instruction max input support" , 16, 23, NIL_IMAGES }, // SKC* + = { { "RDPRU instruction max input support" , 16, 23, NIL_IMAGES }, }; printf(" Feature Extended Size (0x80000008/edx):\n"); @@ -7547,6 +7766,7 @@ { "virtualized global interrupt flag (GIF)" , 16, 16, bools }, { "GMET: guest mode execute trap" , 17, 17, bools }, { "guest Spec_ctl support" , 20, 20, bools }, + { "INVLPGB/TLBSYNC hyperv interc enable" , 24, 24, bools }, }; printf(" SVM Secure Virtual Machine (0x8000000a/edx):\n"); @@ -8385,8 +8605,10 @@ printf(" Direct Cache Access Parameters (9):\n"); printf(" PLATFORM_DCA_CAP MSR bits = %u\n", words[WORD_EAX]); } else if (reg == 0xa) { + printf(" Architecture Performance Monitoring Features (0xa):\n"); print_a_eax(words[WORD_EAX]); print_a_ebx(words[WORD_EBX]); + print_a_ecx(words[WORD_ECX]); print_a_edx(words[WORD_EDX]); } else if (reg == 0xb) { if (try == 0) { @@ -8545,8 +8767,13 @@ printf(" number of sets = 0x%08x (%u)\n", words[WORD_ECX], words[WORD_ECX]); print_18_n_edx(words[WORD_EDX]); + } else if (reg == 0x19) { + printf(" Key Locker information (0x19):\n"); + print_19_eax(words[WORD_EAX]); + print_19_ebx(words[WORD_EBX]); + print_19_ecx(words[WORD_ECX]); } else if (reg == 0x1a) { - printf(" Hybrid Information (0x1a/0)\n"); + printf(" Hybrid Information (0x1a/0):\n"); print_1a_0_eax(words[WORD_EAX]); } else if (reg == 0x1b) { printf(" PCONFIG information (0x1b/n):\n"); @@ -8557,6 +8784,23 @@ 3 * try + 2, words[WORD_ECX], words[WORD_ECX]); printf(" identifier of target %d = 0x%08x (%u)\n", 3 * try + 3, words[WORD_EDX], words[WORD_EDX]); + } else if (reg == 0x1c) { + printf(" Architectural LBR Capabilities (0x1c/0):\n"); + print_1c_eax(words[WORD_EAX]); + print_1c_ebx(words[WORD_EBX]); + print_1c_ecx(words[WORD_ECX]); + } else if (reg == 0x1d) { + if (try == 0) { + printf(" max_palette = %u\n", words[WORD_EAX]); + } else { + printf(" --- palette %d ---\n", try); + print_1d_n_eax(words[WORD_EAX]); + print_1d_n_ebx(words[WORD_EBX]); + print_1d_n_ecx(words[WORD_ECX]); + } + } else if (reg == 0x1e) { + printf(" TMUL Information (0x1e/0):\n"); + print_1e_ebx(words[WORD_EBX]); } else if (reg == 0x1f) { if (try == 0) { // This is invariant across subleaves, so print it only once @@ -8567,6 +8811,12 @@ print_b_1f_ecx(words[WORD_ECX]); print_b_1f_eax(words[WORD_EAX]); print_b_1f_ebx(words[WORD_EBX]); + } else if (reg == 0x20) { + if (try == 0) { + print_20_ebx(words[WORD_EBX]); + } else { + print_reg_raw(reg, try, words); + } } else if (reg == 0x20000000) { // max already set to words[WORD_EAX] } else if (reg == 0x20000001) { @@ -9006,6 +9256,7 @@ boolean quiet) { if (cpuid_fd == USE_INSTRUCTION) { + bzero(words, sizeof(unsigned int)*WORD_NUM); #ifdef USE_CPUID_COUNT __cpuid_count(reg, ecx, words[WORD_EAX], @@ -9098,8 +9349,12 @@ printf(" extended feature flags (7):\n"); } else if (reg == 0xb && try == 0) { printf(" x2APIC features / processor topology (0xb):\n"); + } else if (reg == 0x1d && try == 0) { + printf(" Tile Information (0x1d/0):\n"); } else if (reg == 0x1f && try == 0) { printf(" V2 extended topology (0x1f):\n"); + } else if (reg == 0x20 && try == 0) { + printf(" Processor History Reset information (0x20):\n"); } else if (reg == 0x40000003 && try == 0) { printf(" hypervisor time features (0x40000003/00):\n"); } else if (reg == 0x40000003 && try == 1) { @@ -9319,6 +9574,19 @@ if (try > max_tries) break; real_get(cpuid_fd, reg, words, try, FALSE); } + } else if (reg == 0x1d) { + unsigned int try = 0; + unsigned int max_tries; + for (;;) { + print_header(reg, try, raw); + print_reg(reg, words, raw, try, &stash); + if (try == 0) { + max_tries = words[WORD_EAX]; + } + try++; + if (try > max_tries) break; + real_get(cpuid_fd, reg, words, try, FALSE); + } } else if (reg == 0x1f) { print_header(reg, 0, raw); print_reg(reg, words, raw, 0, &stash); @@ -9328,6 +9596,19 @@ print_reg(reg, words, raw, try, &stash); if (BIT_EXTRACT_LE(words[WORD_ECX], 8, 16) == 0) break; } + } else if (reg == 0x20) { + unsigned int try = 0; + unsigned int max_tries; + for (;;) { + print_header(reg, try, raw); + print_reg(reg, words, raw, try, &stash); + if (try == 0) { + max_tries = words[WORD_EAX]; + } + try++; + if (try > max_tries) break; + real_get(cpuid_fd, reg, words, try, FALSE); + } } else { print_reg(reg, words, raw, 0, &stash); } @@ -9383,6 +9664,15 @@ if (reg == 0x20000000) { max = words[WORD_EAX]; + if (max > 0x20000100) { + // Pentium 4 (and probably many early CPUs) don't support this + // leaf correctly and return garbage (which appears to be a + // replica of the values for the last valid leaf in the + // 0x0xxxxxxx range). As a sanity check to avoid an absurdly + // long dump, if the value obviously is out-of-range, just + // disable all further 0x2xxxxxxx leaves. + max = 0x20000000; + } } print_reg(reg, words, raw, 0, &stash); diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20200427/cpuid.man new/cpuid-20201006/cpuid.man --- old/cpuid-20200427/cpuid.man 2020-04-27 14:10:13.000000000 +0200 +++ new/cpuid-20201006/cpuid.man 2020-10-06 14:39:11.000000000 +0200 @@ -1,7 +1,7 @@ .\" -.\" $Id: cpuid.man,v 20200211 2020/04/27 06:09:42 todd $ +.\" $Id: cpuid.man,v 20201006 2020/10/06 06:38:56 todd $ .\" -.TH CPUID 1 "27 Apr 2020" "20200427" +.TH CPUID 1 "6 Oct 2020" "20201006" .SH NAME cpuid \- Dump CPUID information for each CPU .SH SYNOPSIS @@ -472,8 +472,13 @@ .br 335718: Intel Xeon Processor E3-1200 v6 Product Family Specification Update .br +335864: Intel Celeron Processor J1800, J1900, N2807, and N2930 for +Internet of Things Specification Update Addendum +.br 335901: Intel Core X-Series Processor Family Specification Update .br +336065: Intel Xeon Processor Scalable Family Specification Update +.br 336345: Intel Atom Processor C3000 Product Family Specification Update .br 336466: 8th Generation Intel Processor Family for S-Processor Platforms @@ -499,6 +504,8 @@ .br 615213: 10th Generation Intel Core Processor Specification Update .br +631123: 11th Generation Intel Core Processor Family Specification Update +.br Intel Microcode Update Guidance .RE @@ -582,6 +589,12 @@ .br 55766: Secure Encrypted Virtualization API Version 0.16 Technical Preview .br +55772-A1: Processor Programming Reference (PPR) for AMD Family 17h Model 20h, +Revision A1 Processors +.br +55922-A1: Processor Programming Reference (PPR) for AMD Family 17h Model 60h, +Revision A1 Processors +.br 55803: Preliminary Processor Programming Reference (PPR) for AMD Family 17h Model 31h, Revision B0 Processors .br diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20200427/cpuid.spec new/cpuid-20201006/cpuid.spec --- old/cpuid-20200427/cpuid.spec 2020-04-27 14:11:59.000000000 +0200 +++ new/cpuid-20201006/cpuid.spec 2020-10-06 14:41:56.000000000 +0200 @@ -1,4 +1,4 @@ -%define version 20200427 +%define version 20201006 %define release 1 Summary: dumps CPUID information about the CPU(s) Name: cpuid
