Hello community,
here is the log from the commit of package gmmlib for openSUSE:Factory checked
in at 2020-10-13 15:44:52
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Comparing /work/SRC/openSUSE:Factory/gmmlib (Old)
and /work/SRC/openSUSE:Factory/.gmmlib.new.3486 (New)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "gmmlib"
Tue Oct 13 15:44:52 2020 rev:11 rq:841333 version:20.3.2
Changes:
--------
--- /work/SRC/openSUSE:Factory/gmmlib/gmmlib.changes 2020-09-01
20:10:00.060666290 +0200
+++ /work/SRC/openSUSE:Factory/.gmmlib.new.3486/gmmlib.changes 2020-10-13
15:45:58.605458282 +0200
@@ -1,0 +2,13 @@
+Sat Oct 10 20:53:48 UTC 2020 - Dirk Mueller <dmuel...@suse.com>
+
+- update to 20.3.2
+ * baseAlignment can be greater than 64KB and needs to be aligned to 64KB
+ * DG1 HiZ H/V Align modification
+ * Set MOCS0 with WB cache value
+ * DG1 Placed resource alignment issues Dx12/Vulkan
+ * Remove '-Werror=implicit-function-declaration'
+ * SyncInfoLin: Initialize members
+ * Do not use memset for clearing an object of non-trivial type
+ * Added the ADL-S device ID's and phyAddr support
+
+-------------------------------------------------------------------
Old:
----
intel-gmmlib-20.2.5.tar.gz
New:
----
intel-gmmlib-20.3.2.tar.gz
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Other differences:
------------------
++++++ gmmlib.spec ++++++
--- /var/tmp/diff_new_pack.q283gP/_old 2020-10-13 15:45:59.193458535 +0200
+++ /var/tmp/diff_new_pack.q283gP/_new 2020-10-13 15:45:59.197458537 +0200
@@ -19,7 +19,7 @@
%global somajor 11
%global libname libigdgmm%{somajor}
Name: gmmlib
-Version: 20.2.5
+Version: 20.3.2
Release: 0
Summary: Intel(R) Graphics Memory Management Library Package
License: MIT
++++++ intel-gmmlib-20.2.5.tar.gz -> intel-gmmlib-20.3.2.tar.gz ++++++
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/gmmlib-intel-gmmlib-20.2.5/Source/GmmLib/CachePolicy/GmmGen11CachePolicy.cpp
new/gmmlib-intel-gmmlib-20.3.2/Source/GmmLib/CachePolicy/GmmGen11CachePolicy.cpp
---
old/gmmlib-intel-gmmlib-20.2.5/Source/GmmLib/CachePolicy/GmmGen11CachePolicy.cpp
2020-08-21 19:13:03.000000000 +0200
+++
new/gmmlib-intel-gmmlib-20.3.2/Source/GmmLib/CachePolicy/GmmGen11CachePolicy.cpp
2020-09-14 08:43:35.000000000 +0200
@@ -321,7 +321,6 @@
}
// Explicit MOCS Table
// Index ESC SCC L3CC LeCC TC LRUM
DAoM ERSC SCC PFM SCF CoS SSE
- GMM_DEFINE_MOCS( 0 , 0 , 0 , 1 , 1 , 1 , 0 ,
0 , 0 , 0 , 0 , 0 , 0 , 0 )
GMM_DEFINE_MOCS( 1 , 0 , 0 , 3 , 0 , 1 , 0 ,
0 , 0 , 0 , 0 , 0 , 0 , 0 )
GMM_DEFINE_MOCS( 2 , 0 , 0 , 3 , 3 , 1 , 3 ,
0 , 0 , 0 , 0 , 0 , 0 , 0 )
GMM_DEFINE_MOCS( 3 , 0 , 0 , 1 , 1 , 1 , 0 ,
0 , 0 , 0 , 0 , 0 , 0 , 0 )
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/gmmlib-intel-gmmlib-20.2.5/Source/GmmLib/CachePolicy/GmmGen12CachePolicy.cpp
new/gmmlib-intel-gmmlib-20.3.2/Source/GmmLib/CachePolicy/GmmGen12CachePolicy.cpp
---
old/gmmlib-intel-gmmlib-20.2.5/Source/GmmLib/CachePolicy/GmmGen12CachePolicy.cpp
2020-08-21 19:13:03.000000000 +0200
+++
new/gmmlib-intel-gmmlib-20.3.2/Source/GmmLib/CachePolicy/GmmGen12CachePolicy.cpp
2020-09-14 08:43:35.000000000 +0200
@@ -642,7 +642,6 @@
// Fixed MOCS Table
// Index ESC SCC L3CC LeCC TC LRUM
DAoM ERSC SCC PFM SCF CoS SSE HDCL1
- GMM_DEFINE_MOCS( 0 , 0 , 0 , 1 , 1 , 1 , 0 ,
0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 )
GMM_DEFINE_MOCS( 1 , 0 , 0 , 0 , 0 , 0 , 0 ,
0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 )
GMM_DEFINE_MOCS( 2 , 0 , 0 , 3 , 3 , 1 , 3 ,
0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 )
GMM_DEFINE_MOCS( 3 , 0 , 0 , 1 , 1 , 1 , 0 ,
0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 )
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/gmmlib-intel-gmmlib-20.2.5/Source/GmmLib/CachePolicy/GmmGen12dGPUCachePolicy.cpp
new/gmmlib-intel-gmmlib-20.3.2/Source/GmmLib/CachePolicy/GmmGen12dGPUCachePolicy.cpp
---
old/gmmlib-intel-gmmlib-20.2.5/Source/GmmLib/CachePolicy/GmmGen12dGPUCachePolicy.cpp
2020-08-21 19:13:03.000000000 +0200
+++
new/gmmlib-intel-gmmlib-20.3.2/Source/GmmLib/CachePolicy/GmmGen12dGPUCachePolicy.cpp
2020-09-14 08:43:35.000000000 +0200
@@ -299,7 +299,6 @@
}
// Fixed MOCS Table
// Index ESC SCC L3CC HDCL1
- GMM_DEFINE_MOCS( 0 , 0 , 0 , 1 , 0 )
GMM_DEFINE_MOCS( 1 , 0 , 0 , 1 , 0 )
GMM_DEFINE_MOCS( 2 , 0 , 0 , 0 , 0 )
GMM_DEFINE_MOCS( 3 , 0 , 0 , 0 , 0 )
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/gmmlib-intel-gmmlib-20.2.5/Source/GmmLib/Linux.cmake
new/gmmlib-intel-gmmlib-20.3.2/Source/GmmLib/Linux.cmake
--- old/gmmlib-intel-gmmlib-20.2.5/Source/GmmLib/Linux.cmake 2020-08-21
19:13:03.000000000 +0200
+++ new/gmmlib-intel-gmmlib-20.3.2/Source/GmmLib/Linux.cmake 2020-09-14
08:43:35.000000000 +0200
@@ -34,7 +34,6 @@
-Wno-parentheses
-Wno-missing-braces
-Wno-sign-compare
- -Werror=implicit-function-declaration
-Werror=address
-Werror=format-security
-Werror=non-virtual-dtor
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/gmmlib-intel-gmmlib-20.2.5/Source/GmmLib/Platform/GmmGen12Platform.cpp
new/gmmlib-intel-gmmlib-20.3.2/Source/GmmLib/Platform/GmmGen12Platform.cpp
--- old/gmmlib-intel-gmmlib-20.2.5/Source/GmmLib/Platform/GmmGen12Platform.cpp
2020-08-21 19:13:03.000000000 +0200
+++ new/gmmlib-intel-gmmlib-20.3.2/Source/GmmLib/Platform/GmmGen12Platform.cpp
2020-09-14 08:43:35.000000000 +0200
@@ -115,6 +115,11 @@
Data.ReconMaxHeight = GMM_KBYTE(48);
Data.ReconMaxWidth = GMM_KBYTE(32);
+ if((GFX_GET_CURRENT_PRODUCT(Data.Platform) >= IGFX_DG1))
+ {
+ Data.HiZPixelsPerByte = 4;
+ }
+
Data.TexAlign.Depth.Width = 8; // Not D16_UNORM
Data.TexAlign.Depth.Height = 4;
Data.TexAlign.Depth_D16_UNORM_1x_4x_16x.Width = 8;
@@ -252,6 +257,11 @@
// clang-format on
Data.NoOfBitsSupported = 39;
Data.HighestAcceptablePhysicalAddress = GFX_MASK_LARGE(0, 38);
+ if(GFX_GET_CURRENT_PRODUCT(Data.Platform) == IGFX_ALDERLAKE_S)
+ {
+ Data.NoOfBitsSupported = 46;
+ Data.HighestAcceptablePhysicalAddress = GFX_MASK_LARGE(0, 45);
+ }
}
void GmmLib::PlatformInfoGen12::ApplyExtendedTexAlign(uint32_t CCSMode,
ALIGNMENT &UnitAlign)
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/gmmlib-intel-gmmlib-20.2.5/Source/GmmLib/Resource/GmmResourceInfoCommon.cpp
new/gmmlib-intel-gmmlib-20.3.2/Source/GmmLib/Resource/GmmResourceInfoCommon.cpp
---
old/gmmlib-intel-gmmlib-20.2.5/Source/GmmLib/Resource/GmmResourceInfoCommon.cpp
2020-08-21 19:13:03.000000000 +0200
+++
new/gmmlib-intel-gmmlib-20.3.2/Source/GmmLib/Resource/GmmResourceInfoCommon.cpp
2020-09-14 08:43:35.000000000 +0200
@@ -55,6 +55,7 @@
if(pGmmGlobalContext->GetSkuTable().FtrLocalMemory)
{
Ignore64KBPadding |= (Surf.Flags.Info.NonLocalOnly ||
(Surf.Flags.Info.Shared && !Surf.Flags.Info.NotLockable));
+ Ignore64KBPadding |=
(pGmmGlobalContext->GetSkuTable().FtrLocalMemoryAllows4KB &&
Surf.Flags.Info.NoOptimizationPadding);
}
else
{
@@ -346,7 +347,8 @@
if(Is64KBPageSuitable() && pGmmGlobalContext->GetSkuTable().FtrLocalMemory)
{
- Surf.Alignment.BaseAlignment = GMM_KBYTE(64);
+ // BaseAlignment can be greater than 64KB and needs to be aligned to
64KB
+ Surf.Alignment.BaseAlignment =
GFX_MAX(GFX_ALIGN(Surf.Alignment.BaseAlignment, GMM_KBYTE(64)), GMM_KBYTE(64));
}
GMM_DPF_EXIT;
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/gmmlib-intel-gmmlib-20.2.5/Source/GmmLib/TranslationTable/GmmUmdTranslationTable.h
new/gmmlib-intel-gmmlib-20.3.2/Source/GmmLib/TranslationTable/GmmUmdTranslationTable.h
---
old/gmmlib-intel-gmmlib-20.2.5/Source/GmmLib/TranslationTable/GmmUmdTranslationTable.h
2020-08-21 19:13:03.000000000 +0200
+++
new/gmmlib-intel-gmmlib-20.3.2/Source/GmmLib/TranslationTable/GmmUmdTranslationTable.h
2020-09-14 08:43:35.000000000 +0200
@@ -429,7 +429,7 @@
const int NodesPerTable; //Aux L2/L3 has 32KB size,
Aux L1 has 4KB -can't use as selector for PageTable is AuxTT
// 1 node for TR-table, 8
nodes for Aux-Table L2, 2 nodes for Aux-table L1
//Root Table structure
- struct
+ struct RootTable
{
GMM_RESOURCE_INFO* pGmmResInfo;
HANDLE L3Handle;
@@ -437,6 +437,7 @@
GMM_GFX_ADDRESS CPUAddress; //LMEM-cpuvisible adr
bool NeedRegisterUpdate; //True @ L3 allocation,
False when L3AdrRegWrite done
SyncInfo BBInfo;
+ RootTable() : pGmmResInfo(NULL), L3Handle(NULL), GfxAddress(0),
CPUAddress(0), NeedRegisterUpdate(false), BBInfo() {}
} TTL3;
MidLevelTable* pTTL2; //array of L2-Tables
@@ -455,8 +456,6 @@
NodesPerTable(Size / PAGE_SIZE),
TTType(flag)
{
- memset(&TTL3, 0, sizeof(TTL3));
-
InitializeCriticalSection(&TTLock);
pTTL2 = new MidLevelTable[NumL3e];
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/gmmlib-intel-gmmlib-20.2.5/Source/GmmLib/inc/External/Common/GmmPageTableMgr.h
new/gmmlib-intel-gmmlib-20.3.2/Source/GmmLib/inc/External/Common/GmmPageTableMgr.h
---
old/gmmlib-intel-gmmlib-20.2.5/Source/GmmLib/inc/External/Common/GmmPageTableMgr.h
2020-08-21 19:13:03.000000000 +0200
+++
new/gmmlib-intel-gmmlib-20.3.2/Source/GmmLib/inc/External/Common/GmmPageTableMgr.h
2020-09-14 08:43:35.000000000 +0200
@@ -71,8 +71,8 @@
public:
HANDLE BBQueueHandle;
uint64_t BBFence;
- SyncInfoLin() {}
- SyncInfoLin(HANDLE Handle, uint64_t Fence) {}
+ SyncInfoLin() : BBQueueHandle(NULL), BBFence(0) {}
+ SyncInfoLin(HANDLE Handle, uint64_t Fence) : BBQueueHandle(Handle),
BBFence(Fence) {}
};
typedef class SyncInfoLin SyncInfo;
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/gmmlib-intel-gmmlib-20.2.5/Source/inc/common/igfxfmid.h
new/gmmlib-intel-gmmlib-20.3.2/Source/inc/common/igfxfmid.h
--- old/gmmlib-intel-gmmlib-20.2.5/Source/inc/common/igfxfmid.h 2020-08-21
19:13:03.000000000 +0200
+++ new/gmmlib-intel-gmmlib-20.3.2/Source/inc/common/igfxfmid.h 2020-09-14
08:43:35.000000000 +0200
@@ -68,6 +68,7 @@
IGFX_TIGERLAKE_LP,
IGFX_ROCKETLAKE,
+ IGFX_ALDERLAKE_S,
IGFX_DG1 = 1210,
@@ -97,6 +98,7 @@
PCH_CMP_H, // CML Halo PCH
PCH_CMP_V, // CML V PCH
PCH_JSP_N, // JSL N PCH Device IDs for JSL+ Rev02
+ PCH_ADL_S, // ADL_S PCH
PCH_PRODUCT_FAMILY_FORCE_ULONG = 0x7fffffff
} PCH_PRODUCT_FAMILY;
@@ -1235,6 +1237,18 @@
#define DEV_ID_4E71 0x4E71
#define DEV_ID_4E55 0x4E55
+//ADL-S PCH Device IDs
+#define DEV_ID_4680 0x4680
+#define DEV_ID_4681 0x4681
+#define DEV_ID_4682 0x4682
+#define DEV_ID_4683 0x4683
+#define DEV_ID_4690 0x4690
+#define DEV_ID_4691 0x4691
+#define DEV_ID_4692 0x4692
+#define DEV_ID_4693 0x4693
+#define DEV_ID_4698 0x4698
+#define DEV_ID_4699 0x4699
+
//ICL PCH LP Device IDs
#define ICP_LP_RESERVED_FUSE_ID 0x3480
#define ICP_LP_U_SUPER_SKU_ID 0x3481
